Commit f7eb0c55 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-radeon-fusion' of ../drm-radeon-next into drm-core-next 

* 'drm-radeon-fusion' of ../drm-radeon-next:
  drm/radeon/kms: add Ontario APU ucode loading support
  drm/radeon/kms: add Ontario Fusion APU pci ids
  drm/radeon/kms: enable MSIs on fusion APUs
  drm/radeon/kms: add power table parsing support for Ontario fusion APUs
  drm/radeon/kms: refactor atombios power state fetching
  drm/radeon/kms: add bo blit support for Ontario fusion APUs
  drm/radeon/kms: add thermal sensor support for fusion APUs
  drm/radeon/kms: fill in GPU init for AMD Ontario Fusion APUs
  drm/radeon/kms: add radeon_asic struct for AMD Ontario fusion APUs
  drm/radeon/kms: evergreen.c updates for fusion
  drm/radeon/kms: MC setup changes for fusion APUs
  drm/radeon/kms: move r7xx/evergreen to its own vram_gtt setup function
  drm/radeon/kms: add support for ss overrides on Fusion APUs
  drm/radeon/kms: Add support for external encoders on fusion APUs
  drm/radeon/kms: atom changes for DCE4.1 devices
  drm/radeon/kms: add new family id for AMD Ontario APUs
  drm/radeon/kms: upstream power table updates
  drm/radeon/kms: upstream atombios.h updates
  drm/radeon/kms: upstream ObjectID.h updates
  drm/radeon/kms: setup mc chremap properly on r7xx/evergreen
parents 7e76c5cf 439bd6cd

drivers/gpu/drm/radeon/ObjectID.h

+48 −0
Original line number Diff line number Diff line
@@ -37,6 +37,8 @@ 
#define GRAPH_OBJECT_TYPE_CONNECTOR               0x3

#define GRAPH_OBJECT_TYPE_ROUTER                  0x4

/* deleted */

#define GRAPH_OBJECT_TYPE_DISPLAY_PATH            0x6  

#define GRAPH_OBJECT_TYPE_GENERIC                 0x7



/****************************************************/

/* Encoder Object ID Definition                     */
@@ -64,6 +66,9 @@ 
#define ENCODER_OBJECT_ID_VT1623                  0x10

#define ENCODER_OBJECT_ID_HDMI_SI1930             0x11

#define ENCODER_OBJECT_ID_HDMI_INTERNAL           0x12

#define ENCODER_OBJECT_ID_ALMOND                  0x22

#define ENCODER_OBJECT_ID_TRAVIS                  0x23

#define ENCODER_OBJECT_ID_NUTMEG                  0x22

/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */

#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1   0x13

#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1    0x14
@@ -108,6 +113,7 @@ 
#define CONNECTOR_OBJECT_ID_DISPLAYPORT           0x13

#define CONNECTOR_OBJECT_ID_eDP                   0x14

#define CONNECTOR_OBJECT_ID_MXM                   0x15

#define CONNECTOR_OBJECT_ID_LVDS_eDP              0x16



/* deleted */
@@ -124,6 +130,7 @@ 
#define GENERIC_OBJECT_ID_GLSYNC                  0x01

#define GENERIC_OBJECT_ID_PX2_NON_DRIVABLE        0x02

#define GENERIC_OBJECT_ID_MXM_OPM                 0x03

#define GENERIC_OBJECT_ID_STEREO_PIN              0x04        //This object could show up from Misc Object table, it follows ATOM_OBJECT format, and contains one ATOM_OBJECT_GPIO_CNTL_RECORD for the stereo pin



/****************************************************/

/* Graphics Object ENUM ID Definition               */
@@ -360,6 +367,26 @@ 
                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                  ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)



#define ENCODER_ALMOND_ENUM_ID1                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\

                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                  ENCODER_OBJECT_ID_ALMOND << OBJECT_ID_SHIFT)



#define ENCODER_ALMOND_ENUM_ID2                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\

                                                  GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\

                                                  ENCODER_OBJECT_ID_ALMOND << OBJECT_ID_SHIFT)



#define ENCODER_TRAVIS_ENUM_ID1                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\

                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                  ENCODER_OBJECT_ID_TRAVIS << OBJECT_ID_SHIFT)



#define ENCODER_TRAVIS_ENUM_ID2                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\

                                                  GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\

                                                  ENCODER_OBJECT_ID_TRAVIS << OBJECT_ID_SHIFT)



#define ENCODER_NUTMEG_ENUM_ID1                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\

                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                  ENCODER_OBJECT_ID_NUTMEG << OBJECT_ID_SHIFT)



/****************************************************/

/* Connector Object ID definition - Shared with BIOS */

/****************************************************/
@@ -421,6 +448,14 @@ 
                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)



#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID3   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)



#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID4   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)



#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
@@ -512,6 +547,7 @@ 
#define CONNECTOR_7PIN_DIN_ENUM_ID1            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)



#define CONNECTOR_7PIN_DIN_ENUM_ID2            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
@@ -593,6 +629,14 @@ 
                                                 GRAPH_OBJECT_ENUM_ID7 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DAC



#define CONNECTOR_LVDS_eDP_ENUM_ID1            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_LVDS_eDP << OBJECT_ID_SHIFT)



#define CONNECTOR_LVDS_eDP_ENUM_ID2            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\

                                                 CONNECTOR_OBJECT_ID_LVDS_eDP << OBJECT_ID_SHIFT)



/****************************************************/

/* Router Object ID definition - Shared with BIOS   */

/****************************************************/
@@ -621,6 +665,10 @@ 
                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                 GENERIC_OBJECT_ID_MXM_OPM << OBJECT_ID_SHIFT)



#define GENERICOBJECT_STEREO_PIN_ENUM_ID1        (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\

                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

                                                 GENERIC_OBJECT_ID_STEREO_PIN << OBJECT_ID_SHIFT)



/****************************************************/

/* Object Cap definition - Shared with BIOS         */

/****************************************************/

drivers/gpu/drm/radeon/atombios.h

+932 −65

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/radeon/evergreen.c

+207 −90
Original line number Diff line number Diff line
@@ -112,6 +112,14 @@ u32 evergreen_get_temp(struct radeon_device *rdev) 
	return actual_temp * 1000;

}



u32 sumo_get_temp(struct radeon_device *rdev)

{

	u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;

	u32 actual_temp = (temp >> 1) & 0xff;



	return actual_temp * 1000;

}



void evergreen_pm_misc(struct radeon_device *rdev)

{

	int req_ps_idx = rdev->pm.requested_power_state_index;
@@ -943,31 +951,39 @@ static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_sa 
	save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);

	save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);

	save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);

	if (!(rdev->flags & RADEON_IS_IGP)) {

		save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);

		save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);

		save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);

		save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);

	}



	/* Stop all video */

	WREG32(VGA_RENDER_CONTROL, 0);

	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);

	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);

	if (!(rdev->flags & RADEON_IS_IGP)) {

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);

	}

	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

	if (!(rdev->flags & RADEON_IS_IGP)) {

		WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

		WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

		WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

		WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

	}

	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

	if (!(rdev->flags & RADEON_IS_IGP)) {

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

	}



	WREG32(D1VGA_CONTROL, 0);

	WREG32(D2VGA_CONTROL, 0);
@@ -997,6 +1013,7 @@ static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_ 
	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,

	       (u32)rdev->mc.vram_start);



	if (!(rdev->flags & RADEON_IS_IGP)) {

		WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,

		       upper_32_bits(rdev->mc.vram_start));

		WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
@@ -1032,6 +1049,7 @@ static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_ 
		       (u32)rdev->mc.vram_start);

		WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,

		       (u32)rdev->mc.vram_start);

	}



	WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));

	WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
@@ -1047,22 +1065,28 @@ static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_ 
	WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);

	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);

	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);

	if (!(rdev->flags & RADEON_IS_IGP)) {

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);

	}

	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);

	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);

	if (!(rdev->flags & RADEON_IS_IGP)) {

		WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);

		WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);

		WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);

		WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);

	}

	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

	if (!(rdev->flags & RADEON_IS_IGP)) {

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

	}

	WREG32(VGA_RENDER_CONTROL, save->vga_render_control);

}
@@ -1338,6 +1362,7 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 
	switch (rdev->family) {

	case CHIP_CEDAR:

	case CHIP_REDWOOD:

	case CHIP_PALM:

		force_no_swizzle = false;

		break;

	case CHIP_CYPRESS:
@@ -1437,6 +1462,43 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 
	return backend_map;

}



static void evergreen_program_channel_remap(struct radeon_device *rdev)

{

	u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;



	tmp = RREG32(MC_SHARED_CHMAP);

	switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {

	case 0:

	case 1:

	case 2:

	case 3:

	default:

		/* default mapping */

		mc_shared_chremap = 0x00fac688;

		break;

	}



	switch (rdev->family) {

	case CHIP_HEMLOCK:

	case CHIP_CYPRESS:

		tcp_chan_steer_lo = 0x54763210;

		tcp_chan_steer_hi = 0x0000ba98;

		break;

	case CHIP_JUNIPER:

	case CHIP_REDWOOD:

	case CHIP_CEDAR:

	case CHIP_PALM:

	default:

		tcp_chan_steer_lo = 0x76543210;

		tcp_chan_steer_hi = 0x0000ba98;

		break;

	}



	WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);

	WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);

	WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);

}



static void evergreen_gpu_init(struct radeon_device *rdev)

{

	u32 cc_rb_backend_disable = 0;
@@ -1544,6 +1606,27 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
		rdev->config.evergreen.max_hw_contexts = 4;

		rdev->config.evergreen.sq_num_cf_insts = 1;



		rdev->config.evergreen.sc_prim_fifo_size = 0x40;

		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

		break;

	case CHIP_PALM:

		rdev->config.evergreen.num_ses = 1;

		rdev->config.evergreen.max_pipes = 2;

		rdev->config.evergreen.max_tile_pipes = 2;

		rdev->config.evergreen.max_simds = 2;

		rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;

		rdev->config.evergreen.max_gprs = 256;

		rdev->config.evergreen.max_threads = 192;

		rdev->config.evergreen.max_gs_threads = 16;

		rdev->config.evergreen.max_stack_entries = 256;

		rdev->config.evergreen.sx_num_of_sets = 4;

		rdev->config.evergreen.sx_max_export_size = 128;

		rdev->config.evergreen.sx_max_export_pos_size = 32;

		rdev->config.evergreen.sx_max_export_smx_size = 96;

		rdev->config.evergreen.max_hw_contexts = 4;

		rdev->config.evergreen.sq_num_cf_insts = 1;



		rdev->config.evergreen.sc_prim_fifo_size = 0x40;

		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
@@ -1740,6 +1823,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

	WREG32(HDP_ADDR_CONFIG, gb_addr_config);



	evergreen_program_channel_remap(rdev);



	num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;

	grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
@@ -1822,9 +1907,15 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
		      GS_PRIO(2) |

		      ES_PRIO(3));



	if (rdev->family == CHIP_CEDAR)

	switch (rdev->family) {

	case CHIP_CEDAR:

	case CHIP_PALM:

		/* no vertex cache */

		sq_config &= ~VC_ENABLE;

		break;

	default:

		break;

	}



	sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
@@ -1836,10 +1927,15 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);

	sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);



	if (rdev->family == CHIP_CEDAR)

	switch (rdev->family) {

	case CHIP_CEDAR:

	case CHIP_PALM:

		ps_thread_count = 96;

	else

		break;

	default:

		ps_thread_count = 128;

		break;

	}



	sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);

	sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
@@ -1870,10 +1966,15 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |

					  FORCE_EOV_MAX_REZ_CNT(255)));



	if (rdev->family == CHIP_CEDAR)

	switch (rdev->family) {

	case CHIP_CEDAR:

	case CHIP_PALM:

		vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);

	else

		break;

	default:

		vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);

		break;

	}

	vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);

	WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
@@ -1957,12 +2058,18 @@ int evergreen_mc_init(struct radeon_device *rdev) 
	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);

	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);

	/* Setup GPU memory space */

	if (rdev->flags & RADEON_IS_IGP) {

		/* size in bytes on fusion */

		rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);

		rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);

	} else {

		/* size in MB on evergreen */

		rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;

		rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;

	}

	rdev->mc.visible_vram_size = rdev->mc.aper_size;

	rdev->mc.active_vram_size = rdev->mc.visible_vram_size;

	r600_vram_gtt_location(rdev, &rdev->mc);

	r700_vram_gtt_location(rdev, &rdev->mc);

	radeon_update_bandwidth_info(rdev);



	return 0;
@@ -2079,17 +2186,21 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) 
	WREG32(GRBM_INT_CNTL, 0);

	WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

	WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

	if (!(rdev->flags & RADEON_IS_IGP)) {

		WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

		WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

		WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

		WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

	}



	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

	if (!(rdev->flags & RADEON_IS_IGP)) {

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

	}



	WREG32(DACA_AUTODETECT_INT_CONTROL, 0);

	WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
@@ -2205,10 +2316,12 @@ int evergreen_irq_set(struct radeon_device *rdev) 


	WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);

	WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);

	if (!(rdev->flags & RADEON_IS_IGP)) {

		WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);

		WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);

		WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);

		WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);

	}



	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);

	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
@@ -2765,6 +2878,10 @@ static bool evergreen_card_posted(struct radeon_device *rdev) 
	u32 reg;



	/* first check CRTCs */

	if (rdev->flags & RADEON_IS_IGP)

		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);

	else

		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |

			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |

drivers/gpu/drm/radeon/evergreen_blit_kms.c

+25 −2
Original line number Diff line number Diff line
@@ -147,7 +147,8 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) 
	radeon_ring_write(rdev, 0);

	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);



	if (rdev->family == CHIP_CEDAR)

	if ((rdev->family == CHIP_CEDAR) ||

	    (rdev->family == CHIP_PALM))

		cp_set_surface_sync(rdev,

				    PACKET3_TC_ACTION_ENA, 48, gpu_addr);

	else
@@ -331,9 +332,31 @@ set_default_state(struct radeon_device *rdev) 
		num_hs_stack_entries = 85;

		num_ls_stack_entries = 85;

		break;

	case CHIP_PALM:

		num_ps_gprs = 93;

		num_vs_gprs = 46;

		num_temp_gprs = 4;

		num_gs_gprs = 31;

		num_es_gprs = 31;

		num_hs_gprs = 23;

		num_ls_gprs = 23;

		num_ps_threads = 96;

		num_vs_threads = 16;

		num_gs_threads = 16;

		num_es_threads = 16;

		num_hs_threads = 16;

		num_ls_threads = 16;

		num_ps_stack_entries = 42;

		num_vs_stack_entries = 42;

		num_gs_stack_entries = 42;

		num_es_stack_entries = 42;

		num_hs_stack_entries = 42;

		num_ls_stack_entries = 42;

		break;

	}



	if (rdev->family == CHIP_CEDAR)

	if ((rdev->family == CHIP_CEDAR) ||

	    (rdev->family == CHIP_PALM))

		sq_config = 0;

	else

		sq_config = VC_ENABLE;

drivers/gpu/drm/radeon/evergreend.h

+7 −1
Original line number Diff line number Diff line
@@ -164,11 +164,13 @@ 
#define		SE_SC_BUSY					(1 << 29)

#define		SE_DB_BUSY					(1 << 30)

#define		SE_CB_BUSY					(1 << 31)



/* evergreen */

#define	CG_MULT_THERMAL_STATUS				0x740

#define		ASIC_T(x)			        ((x) << 16)

#define		ASIC_T_MASK			        0x7FF0000

#define		ASIC_T_SHIFT			        16

/* APU */

#define	CG_THERMAL_STATUS			        0x678



#define	HDP_HOST_PATH_CNTL				0x2C00

#define	HDP_NONSURFACE_BASE				0x2C04
@@ -180,6 +182,7 @@ 
#define MC_SHARED_CHMAP						0x2004

#define		NOOFCHAN_SHIFT					12

#define		NOOFCHAN_MASK					0x00003000

#define MC_SHARED_CHREMAP					0x2008



#define	MC_ARB_RAMCFG					0x2760

#define		NOOFBANK_SHIFT					0
@@ -348,6 +351,9 @@ 
#define		SYNC_WALKER					(1 << 25)

#define		SYNC_ALIGNER					(1 << 26)



#define	TCP_CHAN_STEER_LO				0x960c

#define	TCP_CHAN_STEER_HI				0x9610



#define	VGT_CACHE_INVALIDATION				0x88C4

#define		CACHE_INVALIDATION(x)				((x) << 0)

#define			VC_ONLY						0

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