Commit f7d48ffc authored by Wasim Khan's avatar Wasim Khan Committed by Shawn Guo
Browse files

arm64: dts: layerscape: Add label to pcie nodes 



Add label to pcie nodes so that they are easy to
refer.

Signed-off-by: default avatarWasim Khan <wasim.khan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 7358e05b

arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts

+1 −1
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ 
	status = "okay";

};



&pcie {

&pcie1 {

	status = "okay";

};

arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi

+3 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Device Tree Include file for Freescale Layerscape-1012A family SoC.

 * Device Tree Include file for NXP Layerscape-1012A family SoC.

 *

 * Copyright 2016 Freescale Semiconductor, Inc.

 * Copyright 2019-2020 NXP

 *

 */
@@ -489,7 +490,7 @@ 
			interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;

		};



		pcie: pcie@3400000 {

		pcie1: pcie@3400000 {

			compatible = "fsl,ls1012a-pcie";

			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */

			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */

arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * Device Tree Include file for NXP Layerscape-1028A family SoC.

 *

 * Copyright 2018 NXP

 * Copyright 2018-2020 NXP

 *

 * Harninder Rai <harninder.rai@nxp.com>

 *
@@ -553,7 +553,7 @@ 
			status = "disabled";

		};



		pcie@3400000 {

		pcie1: pcie@3400000 {

			compatible = "fsl,ls1028a-pcie";

			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */

			       0x80 0x00000000 0x0 0x00002000>; /* configuration space */
@@ -580,7 +580,7 @@ 
			status = "disabled";

		};



		pcie@3500000 {

		pcie2: pcie@3500000 {

			compatible = "fsl,ls1028a-pcie";

			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */

			       0x88 0x00000000 0x0 0x00002000>; /* configuration space */

arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi

+5 −5
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Device Tree Include file for Freescale Layerscape-1043A family SoC.

 * Device Tree Include file for NXP Layerscape-1043A family SoC.

 *

 * Copyright 2014-2015 Freescale Semiconductor, Inc.

 * Copyright 2018 NXP

 * Copyright 2018, 2020 NXP

 *

 * Mingkai Hu <Mingkai.hu@freescale.com>

 */
@@ -814,7 +814,7 @@ 
			interrupts = <0 160 0x4>;

		};



		pcie@3400000 {

		pcie1: pcie@3400000 {

			compatible = "fsl,ls1043a-pcie";

			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */

			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
@@ -840,7 +840,7 @@ 
			status = "disabled";

		};



		pcie@3500000 {

		pcie2: pcie@3500000 {

			compatible = "fsl,ls1043a-pcie";

			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */

			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
@@ -866,7 +866,7 @@ 
			status = "disabled";

		};



		pcie@3600000 {

		pcie3: pcie@3600000 {

			compatible = "fsl,ls1043a-pcie";

			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */

			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */

arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

+8 −8
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Device Tree Include file for Freescale Layerscape-1046A family SoC.

 * Device Tree Include file for NXP Layerscape-1046A family SoC.

 *

 * Copyright 2016 Freescale Semiconductor, Inc.

 * Copyright 2018 NXP

 * Copyright 2018, 2020 NXP

 *

 * Mingkai Hu <mingkai.hu@nxp.com>

 */
@@ -718,7 +718,7 @@ 
				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;

		};



		pcie@3400000 {

		pcie1: pcie@3400000 {

			compatible = "fsl,ls1046a-pcie";

			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */

			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
@@ -744,7 +744,7 @@ 
			status = "disabled";

		};



		pcie_ep@3400000 {

		pcie_ep1: pcie_ep@3400000 {

			compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";

			reg = <0x00 0x03400000 0x0 0x00100000

				0x40 0x00000000 0x8 0x00000000>;
@@ -754,7 +754,7 @@ 
			status = "disabled";

		};



		pcie@3500000 {

		pcie2: pcie@3500000 {

			compatible = "fsl,ls1046a-pcie";

			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */

			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
@@ -780,7 +780,7 @@ 
			status = "disabled";

		};



		pcie_ep@3500000 {

		pcie_ep2: pcie_ep@3500000 {

			compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";

			reg = <0x00 0x03500000 0x0 0x00100000

				0x48 0x00000000 0x8 0x00000000>;
@@ -790,7 +790,7 @@ 
			status = "disabled";

		};



		pcie@3600000 {

		pcie3: pcie@3600000 {

			compatible = "fsl,ls1046a-pcie";

			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */

			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
@@ -816,7 +816,7 @@ 
			status = "disabled";

		};



		pcie_ep@3600000 {

		pcie_ep3: pcie_ep@3600000 {

			compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";

			reg = <0x00 0x03600000 0x0 0x00100000

				0x50 0x00000000 0x8 0x00000000>;

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