clk: aspeed: Add reset controller (f7989839) · Commits · 戴 / test

drivers/clk/clk-aspeed.c

+81 −1

Original line number	Diff line number	Diff line
		@@ -8,6 +8,7 @@
		#include <linux/of_device.h>
		#include <linux/platform_device.h>
		#include <linux/regmap.h>
		#include <linux/reset-controller.h>
		#include <linux/slab.h>
		#include <linux/spinlock.h>

		@@ -267,6 +268,68 @@ static const struct clk_ops aspeed_clk_gate_ops = {
		.is_enabled = aspeed_clk_is_enabled,
		};

		/**
		* struct aspeed_reset - Aspeed reset controller
		* @map: regmap to access the containing system controller
		* @rcdev: reset controller device
		*/
		struct aspeed_reset {
		struct regmap *map;
		struct reset_controller_dev rcdev;
		};

		#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)

		static const u8 aspeed_resets[] = {
		[ASPEED_RESET_XDMA] = 25,
		[ASPEED_RESET_MCTP] = 24,
		[ASPEED_RESET_ADC] = 23,
		[ASPEED_RESET_JTAG_MASTER] = 22,
		[ASPEED_RESET_MIC] = 18,
		[ASPEED_RESET_PWM] = 9,
		[ASPEED_RESET_PCIVGA] = 8,
		[ASPEED_RESET_I2C] = 2,
		[ASPEED_RESET_AHB] = 1,
		};

		static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,
		unsigned long id)
		{
		struct aspeed_reset *ar = to_aspeed_reset(rcdev);
		u32 rst = BIT(aspeed_resets[id]);

		return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0);
		}

		static int aspeed_reset_assert(struct reset_controller_dev *rcdev,
		unsigned long id)
		{
		struct aspeed_reset *ar = to_aspeed_reset(rcdev);
		u32 rst = BIT(aspeed_resets[id]);

		return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst);
		}

		static int aspeed_reset_status(struct reset_controller_dev *rcdev,
		unsigned long id)
		{
		struct aspeed_reset *ar = to_aspeed_reset(rcdev);
		u32 val, rst = BIT(aspeed_resets[id]);
		int ret;

		ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val);
		if (ret)
		return ret;

		return !!(val & rst);
		}

		static const struct reset_control_ops aspeed_reset_ops = {
		.assert = aspeed_reset_assert,
		.deassert = aspeed_reset_deassert,
		.status = aspeed_reset_status,
		};

		static struct clk_hw aspeed_clk_hw_register_gate(struct device dev,
		const char name, const char parent_name, unsigned long flags,
		struct regmap *map, u8 clock_idx, u8 reset_idx,
		@@ -308,10 +371,11 @@ static int aspeed_clk_probe(struct platform_device *pdev)
		{
		const struct aspeed_clk_soc_data *soc_data;
		struct device *dev = &pdev->dev;
		struct aspeed_reset *ar;
		struct regmap *map;
		struct clk_hw *hw;
		u32 val, rate;
		int i;
		int i, ret;

		map = syscon_node_to_regmap(dev->of_node);
		if (IS_ERR(map)) {
		@@ -319,6 +383,22 @@ static int aspeed_clk_probe(struct platform_device *pdev)
		return PTR_ERR(map);
		}

		ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
		if (!ar)
		return -ENOMEM;

		ar->map = map;
		ar->rcdev.owner = THIS_MODULE;
		ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets);
		ar->rcdev.ops = &aspeed_reset_ops;
		ar->rcdev.of_node = dev->of_node;

		ret = devm_reset_controller_register(dev, &ar->rcdev);
		if (ret) {
		dev_err(dev, "could not register reset controller\n");
		return ret;
		}

		/* SoC generations share common layouts but have different divisors */
		soc_data = of_device_get_match_data(dev);
		if (!soc_data) {

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