platform/x86: intel_pmc_core: Change Jasper Lake S0ix debug reg map back to ICL (f78bf066) · Commits · 戴 / test

Jasper Lake uses Icelake PCH IPs and the S0ix debug interfaces are same as Icelake. It uses SLP_S0_DBG register latch/read interface from Icelake generation. It doesn't use Tiger Lake LPM debug registers. Change the Jasper Lake S0ix debug interface to use the ICL reg map. Fixes: ("platform/x86: intel_pmc_core: Add Atom based Jasper Lake (JSL) platform support") Signed-off-by:

Archana Patni <archana.patni@intel.com> Acked-by:

David E. Box <david.e.box@intel.com> Tested-by:

Divagar Mohandass <divagar.mohandass@intel.com> Signed-off-by:

Andy Shevchenko <andriy.shevchenko@linux.intel.com>

drivers/platform/x86/intel_pmc_core.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -255,7 +255,7 @@ static const struct pmc_bit_map *ext_cnp_pfear_map[] = {
		};

		static const struct pmc_bit_map icl_pfear_map[] = {
		/* Ice Lake generation onwards only */
		/* Ice Lake and Jasper Lake generation onwards only */
		{"RES_65", BIT(0)},
		{"RES_66", BIT(1)},
		{"RES_67", BIT(2)},
		@@ -274,7 +274,7 @@ static const struct pmc_bit_map *ext_icl_pfear_map[] = {
		};

		static const struct pmc_bit_map tgl_pfear_map[] = {
		/* Tiger Lake, Elkhart Lake and Jasper Lake generation onwards only */
		/* Tiger Lake and Elkhart Lake generation onwards only */
		{"PSF9", BIT(0)},
		{"RES_66", BIT(1)},
		{"RES_67", BIT(2)},
		@@ -1156,7 +1156,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
		X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &tgl_reg_map),
		X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &tgl_reg_map),
		X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &tgl_reg_map),
		X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &tgl_reg_map),
		X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &icl_reg_map),
		{}
		};

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