Merge branch 'net-mvpp2-cls-Add-classification' (f76c4b57) · Commits · 戴 / test

drivers/net/ethernet/marvell/mvpp2/mvpp2.h

+42 −0

Original line number	Original line	Diff line number	Diff line
	@@ -14,6 +14,7 @@
	#include <linux/netdevice.h>		#include <linux/netdevice.h>
	#include <linux/phy.h>		#include <linux/phy.h>
	#include <linux/phylink.h>		#include <linux/phylink.h>
			#include <net/flow_offload.h>

	/* Fifo Registers */		/* Fifo Registers */
	#define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))		#define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
	@@ -126,6 +127,7 @@
	#define MVPP22_CLS_C2_TCAM_DATA4 0x1b20		#define MVPP22_CLS_C2_TCAM_DATA4 0x1b20
	#define MVPP22_CLS_C2_LU_TYPE(lu) ((lu) & 0x3f)		#define MVPP22_CLS_C2_LU_TYPE(lu) ((lu) & 0x3f)
	#define MVPP22_CLS_C2_PORT_ID(port) ((port) << 8)		#define MVPP22_CLS_C2_PORT_ID(port) ((port) << 8)
			#define MVPP22_CLS_C2_PORT_MASK (0xff << 8)
	#define MVPP22_CLS_C2_TCAM_INV 0x1b24		#define MVPP22_CLS_C2_TCAM_INV 0x1b24
	#define MVPP22_CLS_C2_TCAM_INV_BIT BIT(31)		#define MVPP22_CLS_C2_TCAM_INV_BIT BIT(31)
	#define MVPP22_CLS_C2_HIT_CTR 0x1b50		#define MVPP22_CLS_C2_HIT_CTR 0x1b50
	@@ -134,6 +136,7 @@
	#define MVPP22_CLS_C2_ACT_FWD(act) (((act) & 0x7) << 13)		#define MVPP22_CLS_C2_ACT_FWD(act) (((act) & 0x7) << 13)
	#define MVPP22_CLS_C2_ACT_QHIGH(act) (((act) & 0x3) << 11)		#define MVPP22_CLS_C2_ACT_QHIGH(act) (((act) & 0x3) << 11)
	#define MVPP22_CLS_C2_ACT_QLOW(act) (((act) & 0x3) << 9)		#define MVPP22_CLS_C2_ACT_QLOW(act) (((act) & 0x3) << 9)
			#define MVPP22_CLS_C2_ACT_COLOR(act) ((act) & 0x7)
	#define MVPP22_CLS_C2_ATTR0 0x1b64		#define MVPP22_CLS_C2_ATTR0 0x1b64
	#define MVPP22_CLS_C2_ATTR0_QHIGH(qh) (((qh) & 0x1f) << 24)		#define MVPP22_CLS_C2_ATTR0_QHIGH(qh) (((qh) & 0x1f) << 24)
	#define MVPP22_CLS_C2_ATTR0_QHIGH_MASK 0x1f		#define MVPP22_CLS_C2_ATTR0_QHIGH_MASK 0x1f
	@@ -615,6 +618,10 @@
	#define MVPP2_BIT_IN_WORD(bit) ((bit) % 32)		#define MVPP2_BIT_IN_WORD(bit) ((bit) % 32)

	#define MVPP2_N_PRS_FLOWS 52		#define MVPP2_N_PRS_FLOWS 52
			#define MVPP2_N_RFS_ENTRIES_PER_FLOW 4

			/* There are 7 supported high-level flows */
			#define MVPP2_N_RFS_RULES (MVPP2_N_RFS_ENTRIES_PER_FLOW * 7)

	/* RSS constants */		/* RSS constants */
	#define MVPP22_RSS_TABLE_ENTRIES 32		#define MVPP22_RSS_TABLE_ENTRIES 32
	@@ -812,6 +819,37 @@ struct mvpp2_queue_vector {
	struct cpumask *mask;		struct cpumask *mask;
	};		};

			/* Internal represention of a Flow Steering rule */
			struct mvpp2_rfs_rule {
			/* Rule location inside the flow*/
			int loc;

			/* Flow type, such as TCP_V4_FLOW, IP6_FLOW, etc. */
			int flow_type;

			/* Index of the C2 TCAM entry handling this rule */
			int c2_index;

			/* Header fields that needs to be extracted to match this flow */
			u16 hek_fields;

			/* CLS engine : only c2 is supported for now. */
			u8 engine;

			/* TCAM key and mask for C2-based steering. These fields should be
			* encapsulated in a union should we add more engines.
			*/
			u64 c2_tcam;
			u64 c2_tcam_mask;

			struct flow_rule *flow;
			};

			struct mvpp2_ethtool_fs {
			struct mvpp2_rfs_rule rule;
			struct ethtool_rxnfc rxnfc;
			};

	struct mvpp2_port {		struct mvpp2_port {
	u8 id;		u8 id;

	@@ -883,6 +921,10 @@ struct mvpp2_port {

	/* RSS indirection table */		/* RSS indirection table */
	u32 indir[MVPP22_RSS_TABLE_ENTRIES];		u32 indir[MVPP22_RSS_TABLE_ENTRIES];

			/* List of steering rules active on that port */
			struct mvpp2_ethtool_fs *rfs_rules[MVPP2_N_RFS_RULES];
			int n_rfs_rules;
	};		};

	/* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the		/* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the

drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c

+425 −72

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.h

+59 −11

Original line number	Original line	Diff line number	Diff line
	@@ -92,6 +92,17 @@ enum mvpp22_cls_c2_fwd_action {
	MVPP22_C2_FWD_HW_LOW_LAT_LOCK,		MVPP22_C2_FWD_HW_LOW_LAT_LOCK,
	};		};

			enum mvpp22_cls_c2_color_action {
			MVPP22_C2_COL_NO_UPD = 0,
			MVPP22_C2_COL_NO_UPD_LOCK,
			MVPP22_C2_COL_GREEN,
			MVPP22_C2_COL_GREEN_LOCK,
			MVPP22_C2_COL_YELLOW,
			MVPP22_C2_COL_YELLOW_LOCK,
			MVPP22_C2_COL_RED, /* Drop */
			MVPP22_C2_COL_RED_LOCK, /* Drop */
			};

	#define MVPP2_CLS_C2_TCAM_WORDS 5		#define MVPP2_CLS_C2_TCAM_WORDS 5
	#define MVPP2_CLS_C2_ATTR_WORDS 5		#define MVPP2_CLS_C2_ATTR_WORDS 5

	@@ -107,15 +118,36 @@ struct mvpp2_cls_c2_entry {
	u8 valid;		u8 valid;
	};		};

			#define MVPP22_FLOW_ETHER_BIT BIT(0)
			#define MVPP22_FLOW_IP4_BIT BIT(1)
			#define MVPP22_FLOW_IP6_BIT BIT(2)
			#define MVPP22_FLOW_TCP_BIT BIT(3)
			#define MVPP22_FLOW_UDP_BIT BIT(4)

			#define MVPP22_FLOW_TCP4 (MVPP22_FLOW_ETHER_BIT \| MVPP22_FLOW_IP4_BIT \| MVPP22_FLOW_TCP_BIT)
			#define MVPP22_FLOW_TCP6 (MVPP22_FLOW_ETHER_BIT \| MVPP22_FLOW_IP6_BIT \| MVPP22_FLOW_TCP_BIT)
			#define MVPP22_FLOW_UDP4 (MVPP22_FLOW_ETHER_BIT \| MVPP22_FLOW_IP4_BIT \| MVPP22_FLOW_UDP_BIT)
			#define MVPP22_FLOW_UDP6 (MVPP22_FLOW_ETHER_BIT \| MVPP22_FLOW_IP6_BIT \| MVPP22_FLOW_UDP_BIT)
			#define MVPP22_FLOW_IP4 (MVPP22_FLOW_ETHER_BIT \| MVPP22_FLOW_IP4_BIT)
			#define MVPP22_FLOW_IP6 (MVPP22_FLOW_ETHER_BIT \| MVPP22_FLOW_IP6_BIT)
			#define MVPP22_FLOW_ETHERNET (MVPP22_FLOW_ETHER_BIT)

	/* Classifier C2 engine entries */		/* Classifier C2 engine entries */
	#define MVPP22_CLS_C2_N_ENTRIES 256		#define MVPP22_CLS_C2_N_ENTRIES 256

	/* Number of per-port dedicated entries in the C2 TCAM */		/* Number of per-port dedicated entries in the C2 TCAM */
	#define MVPP22_CLS_C2_PORT_RANGE 8		#define MVPP22_CLS_C2_PORT_N_FLOWS MVPP2_N_RFS_ENTRIES_PER_FLOW

	#define MVPP22_CLS_C2_PORT_FIRST(p) (MVPP22_CLS_C2_N_ENTRIES - \		/* Each port has oen range per flow type + one entry controling the global RSS
	((p) * MVPP22_CLS_C2_PORT_RANGE))		* setting and the default rx queue
	#define MVPP22_CLS_C2_RSS_ENTRY(p) (MVPP22_CLS_C2_PORT_FIRST(p) - 1)		*/
			#define MVPP22_CLS_C2_PORT_RANGE (MVPP22_CLS_C2_PORT_N_FLOWS + 1)
			#define MVPP22_CLS_C2_PORT_FIRST(p) ((p) * MVPP22_CLS_C2_PORT_RANGE)
			#define MVPP22_CLS_C2_RSS_ENTRY(p) (MVPP22_CLS_C2_PORT_FIRST((p) + 1) - 1)

			#define MVPP22_CLS_C2_PORT_FLOW_FIRST(p) (MVPP22_CLS_C2_PORT_FIRST(p))

			#define MVPP22_CLS_C2_RFS_LOC(p, loc) (MVPP22_CLS_C2_PORT_FLOW_FIRST(p) + (loc))

	/* Packet flow ID */		/* Packet flow ID */
	enum mvpp2_prs_flow {		enum mvpp2_prs_flow {
	@@ -145,10 +177,6 @@ enum mvpp2_prs_flow {
	MVPP2_FL_LAST,		MVPP2_FL_LAST,
	};		};

	enum mvpp2_cls_lu_type {
	MVPP2_CLS_LU_ALL = 0,
	};

	/* LU Type defined for all engines, and specified in the flow table */		/* LU Type defined for all engines, and specified in the flow table */
	#define MVPP2_CLS_LU_TYPE_MASK 0x3f		#define MVPP2_CLS_LU_TYPE_MASK 0x3f

	@@ -168,11 +196,16 @@ struct mvpp2_cls_flow {
	struct mvpp2_prs_result_info prs_ri;		struct mvpp2_prs_result_info prs_ri;
	};		};

	#define MVPP2_CLS_FLT_ENTRIES_PER_FLOW (MVPP2_MAX_PORTS + 1)		#define MVPP2_CLS_FLT_ENTRIES_PER_FLOW (MVPP2_MAX_PORTS + 1 + 16)
	#define MVPP2_CLS_FLT_FIRST(id) (((id) - MVPP2_FL_START) * \		#define MVPP2_CLS_FLT_FIRST(id) (((id) - MVPP2_FL_START) * \
	MVPP2_CLS_FLT_ENTRIES_PER_FLOW)		MVPP2_CLS_FLT_ENTRIES_PER_FLOW)
	#define MVPP2_CLS_FLT_C2_RSS_ENTRY(id) (MVPP2_CLS_FLT_FIRST(id))
	#define MVPP2_CLS_FLT_HASH_ENTRY(port, id) (MVPP2_CLS_FLT_C2_RSS_ENTRY(id) + (port) + 1)		#define MVPP2_CLS_FLT_C2_RFS(port, id, rfs_n) (MVPP2_CLS_FLT_FIRST(id) + \
			((port) * MVPP2_MAX_PORTS) + \
			(rfs_n))

			#define MVPP2_CLS_FLT_C2_RSS_ENTRY(id) (MVPP2_CLS_FLT_C2_RFS(MVPP2_MAX_PORTS, id, 0))
			#define MVPP2_CLS_FLT_HASH_ENTRY(port, id) (MVPP2_CLS_FLT_C2_RSS_ENTRY(id) + 1 + (port))
	#define MVPP2_CLS_FLT_LAST(id) (MVPP2_CLS_FLT_FIRST(id) + \		#define MVPP2_CLS_FLT_LAST(id) (MVPP2_CLS_FLT_FIRST(id) + \
	MVPP2_CLS_FLT_ENTRIES_PER_FLOW - 1)		MVPP2_CLS_FLT_ENTRIES_PER_FLOW - 1)

	@@ -199,6 +232,12 @@ struct mvpp2_cls_flow {
	continue; \		continue; \
	else		else

			#define for_each_cls_flow_id_containing_type(i, type) \
			for_each_cls_flow_id((i)) \
			if ((cls_flows[(i)].flow_type & (type)) != (type)) \
			continue; \
			else

	struct mvpp2_cls_flow_entry {		struct mvpp2_cls_flow_entry {
	u32 index;		u32 index;
	u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];		u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
	@@ -246,4 +285,13 @@ u32 mvpp2_cls_c2_hit_count(struct mvpp2 *priv, int c2_index);
	void mvpp2_cls_c2_read(struct mvpp2 *priv, int index,		void mvpp2_cls_c2_read(struct mvpp2 *priv, int index,
	struct mvpp2_cls_c2_entry *c2);		struct mvpp2_cls_c2_entry *c2);

			int mvpp2_ethtool_cls_rule_get(struct mvpp2_port *port,
			struct ethtool_rxnfc *rxnfc);

			int mvpp2_ethtool_cls_rule_ins(struct mvpp2_port *port,
			struct ethtool_rxnfc *info);

			int mvpp2_ethtool_cls_rule_del(struct mvpp2_port *port,
			struct ethtool_rxnfc *info);

	#endif		#endif

drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

+19 −1

Original line number	Original line	Diff line number	Diff line
	@@ -3937,7 +3937,7 @@ static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
	struct ethtool_rxnfc info, u32 rules)		struct ethtool_rxnfc info, u32 rules)
	{		{
	struct mvpp2_port *port = netdev_priv(dev);		struct mvpp2_port *port = netdev_priv(dev);
	int ret = 0;		int ret = 0, i, loc = 0;

	if (!mvpp22_rss_is_supported())		if (!mvpp22_rss_is_supported())
	return -EOPNOTSUPP;		return -EOPNOTSUPP;
	@@ -3949,6 +3949,18 @@ static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
	case ETHTOOL_GRXRINGS:		case ETHTOOL_GRXRINGS:
	info->data = port->nrxqs;		info->data = port->nrxqs;
	break;		break;
			case ETHTOOL_GRXCLSRLCNT:
			info->rule_cnt = port->n_rfs_rules;
			break;
			case ETHTOOL_GRXCLSRULE:
			ret = mvpp2_ethtool_cls_rule_get(port, info);
			break;
			case ETHTOOL_GRXCLSRLALL:
			for (i = 0; i < MVPP2_N_RFS_RULES; i++) {
			if (port->rfs_rules[i])
			rules[loc++] = i;
			}
			break;
	default:		default:
	return -ENOTSUPP;		return -ENOTSUPP;
	}		}
	@@ -3969,6 +3981,12 @@ static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
	case ETHTOOL_SRXFH:		case ETHTOOL_SRXFH:
	ret = mvpp2_ethtool_rxfh_set(port, info);		ret = mvpp2_ethtool_rxfh_set(port, info);
	break;		break;
			case ETHTOOL_SRXCLSRLINS:
			ret = mvpp2_ethtool_cls_rule_ins(port, info);
			break;
			case ETHTOOL_SRXCLSRLDEL:
			ret = mvpp2_ethtool_cls_rule_del(port, info);
			break;
	default:		default:
	return -EOPNOTSUPP;		return -EOPNOTSUPP;
	}		}

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