Commit f75e94d8 authored by Guchun Chen's avatar Guchun Chen Committed by Alex Deucher
Browse files

drm/amdgpu: bypass querying ras error count registers 



Once ras recovery is issued by ras sync flood interrupt or
ras controller interrupt, add this guard to bypass or execute
ras error count register harvest of all IPs.

Signed-off-by: default avatarGuchun Chen <guchun.chen@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarDennis Li <Dennis.Li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0cf0ee98

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+12 −10
Original line number Diff line number Diff line
@@ -1547,16 +1547,18 @@ static void amdgpu_ras_do_recovery(struct work_struct *work) 
	struct list_head device_list, *device_list_handle =  NULL;

	struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, false);



	if (!ras->disable_ras_err_cnt_harvest) {

		/* Build list of devices to query RAS related errors */

	if  (hive && adev->gmc.xgmi.num_physical_nodes > 1)

		if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {

			device_list_handle = &hive->device_list;

	else {

		} else {

			INIT_LIST_HEAD(&device_list);

			list_add_tail(&adev->gmc.xgmi.head, &device_list);

			device_list_handle = &device_list;

		}



	list_for_each_entry(remote_adev, device_list_handle, gmc.xgmi.head) {

		list_for_each_entry(remote_adev,

				device_list_handle, gmc.xgmi.head)

			amdgpu_ras_log_on_err_counter(remote_adev);

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

+3 −0
Original line number Diff line number Diff line
@@ -343,6 +343,9 @@ struct amdgpu_ras { 


	/* bad page count threshold */

	uint32_t bad_page_cnt_threshold;



	/* disable ras error count harvest in recovery */

	bool disable_ras_err_cnt_harvest;

};



struct ras_fs_data {

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

+26 −22
Original line number Diff line number Diff line
@@ -302,6 +302,7 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device 
	uint32_t bif_doorbell_intr_cntl;

	struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);

	struct ras_err_data err_data = {0, 0, 0, NULL};

	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);



	bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);

	if (REG_GET_FIELD(bif_doorbell_intr_cntl,
@@ -312,13 +313,15 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device 
						RAS_CNTLR_INTERRUPT_CLEAR, 1);

		WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);



		if (!ras->disable_ras_err_cnt_harvest) {

			/*

		 * clear error status after ras_controller_intr according to

		 * hw team and count ue number for query

			 * clear error status after ras_controller_intr

			 * according to hw team and count ue number

			 * for query

			 */

			nbio_v7_4_query_ras_error_count(adev, &err_data);



		/* logging on error counter and printing for awareness */

			/* logging on error cnt and printing for awareness */

			obj->err_data.ue_count += err_data.ue_count;

			obj->err_data.ce_count += err_data.ce_count;
@@ -334,6 +337,7 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device 
						"errors detected in %s block\n",

						obj->err_data.ue_count,

						adev->nbio.ras_if->name);

		}



		dev_info(adev->dev, "RAS controller interrupt triggered "

					"by NBIF error\n");

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