Commit f735c40e authored by Andre Przywara's avatar Andre Przywara Committed by David S. Miller
Browse files

net: axienet: Autodetect 64-bit DMA capability 



When newer revisions of the Axienet IP are configured for a 64-bit bus,
we *need* to write to the MSB part of the an address registers,
otherwise the IP won't recognise this as a DMA start condition.
This is even true when the actual DMA address comes from the lower 4 GB.

To autodetect this configuration, at probe time we write all 1's to such
an MSB register, and see if any bits stick. If this is configured for a
32-bit bus, those MSB registers are RES0, so reading back 0 indicates
that no MSB writes are necessary.
On the other hands reading anything other than 0 indicated the need to
write the MSB registers, so we set the respective flag.

The actual DMA mask stays at 32-bit for now. To help bisecting, a
separate patch will enable allocations from higher addresses.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 4e958f33

drivers/net/ethernet/xilinx/xilinx_axienet.h

+1 −0
Original line number Diff line number Diff line
@@ -161,6 +161,7 @@ 
#define XAE_FCC_OFFSET		0x0000040C /* Flow Control Configuration */

#define XAE_EMMC_OFFSET		0x00000410 /* EMAC mode configuration */

#define XAE_PHYC_OFFSET		0x00000414 /* RGMII/SGMII configuration */

#define XAE_ID_OFFSET		0x000004F8 /* Identification register */

#define XAE_MDIO_MC_OFFSET	0x00000500 /* MII Management Config */

#define XAE_MDIO_MCR_OFFSET	0x00000504 /* MII Management Control */

#define XAE_MDIO_MWD_OFFSET	0x00000508 /* MII Management Write Data */

drivers/net/ethernet/xilinx/xilinx_axienet_main.c

+26 −0
Original line number Diff line number Diff line
@@ -151,6 +151,9 @@ static void axienet_dma_out_addr(struct axienet_local *lp, off_t reg, 
				 dma_addr_t addr)

{

	axienet_dma_out32(lp, reg, lower_32_bits(addr));



	if (lp->features & XAE_FEATURE_DMA_64BIT)

		axienet_dma_out32(lp, reg + 4, upper_32_bits(addr));

}



static void desc_set_phys_addr(struct axienet_local *lp, dma_addr_t addr,
@@ -1928,6 +1931,29 @@ static int axienet_probe(struct platform_device *pdev) 
		goto free_netdev;

	}



	/* Autodetect the need for 64-bit DMA pointers.

	 * When the IP is configured for a bus width bigger than 32 bits,

	 * writing the MSB registers is mandatory, even if they are all 0.

	 * We can detect this case by writing all 1's to one such register

	 * and see if that sticks: when the IP is configured for 32 bits

	 * only, those registers are RES0.

	 * Those MSB registers were introduced in IP v7.1, which we check first.

	 */

	if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) {

		void __iomem *desc = lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4;



		iowrite32(0x0, desc);

		if (ioread32(desc) == 0) {	/* sanity check */

			iowrite32(0xffffffff, desc);

			if (ioread32(desc) > 0) {

				lp->features |= XAE_FEATURE_DMA_64BIT;

				dev_info(&pdev->dev,

					 "autodetected 64-bit DMA range\n");

			}

			iowrite32(0x0, desc);

		}

	}



	/* Check for Ethernet core IRQ (optional) */

	if (lp->eth_irq <= 0)

		dev_info(&pdev->dev, "Ethernet core IRQ not defined\n");

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