drm/amdgpu: move waiting for VM flush into gmc_v9_0_emit_flush_gpu_tlb (f732b6b3) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+9 −10

Original line number	Diff line number	Diff line
		@@ -3679,15 +3679,8 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
		unsigned vmid, unsigned pasid,
		uint64_t pd_addr)
		{
		struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
		unsigned eng = ring->vm_inv_eng;

		amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);

		/* wait for the invalidate to complete */
		gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack + eng,
		0, 1 << vmid, 1 << vmid, 0x20);

		/* compute doesn't have PFP */
		if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
		/* sync PFP to ME, otherwise we might get invalid PFP reads */
		@@ -4295,7 +4288,9 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
		.emit_frame_size = /* totally 242 maximum if 16 IBs */
		5 + /* COND_EXEC */
		7 + /* PIPELINE_SYNC */
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
		2 + /* VM_FLUSH */
		8 + /* FENCE for VM_FLUSH */
		20 + /* GDS switch */
		4 + /* double SWITCH_BUFFER,
		@@ -4344,7 +4339,9 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
		7 + /* gfx_v9_0_ring_emit_hdp_flush */
		5 + /* hdp invalidate */
		7 + /* gfx_v9_0_ring_emit_pipeline_sync */
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* gfx_v9_0_ring_emit_vm_flush */
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
		2 + /* gfx_v9_0_ring_emit_vm_flush */
		8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
		.emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
		.emit_ib = gfx_v9_0_ring_emit_ib_compute,
		@@ -4376,7 +4373,9 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
		7 + /* gfx_v9_0_ring_emit_hdp_flush */
		5 + /* hdp invalidate */
		7 + /* gfx_v9_0_ring_emit_pipeline_sync */
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* gfx_v9_0_ring_emit_vm_flush */
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
		2 + /* gfx_v9_0_ring_emit_vm_flush */
		8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
		.emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
		.emit_ib = gfx_v9_0_ring_emit_ib_compute,

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -396,6 +396,10 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,

		amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);

		/* wait for the invalidate to complete */
		amdgpu_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng,
		1 << vmid, 1 << vmid);

		return pd_addr;
		}

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+3 −15

Original line number	Diff line number	Diff line
		@@ -1126,21 +1126,7 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
		unsigned vmid, unsigned pasid,
		uint64_t pd_addr)
		{
		struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
		unsigned eng = ring->vm_inv_eng;

		amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);

		/* wait for flush */
		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) \|
		SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) \|
		SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
		amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
		amdgpu_ring_write(ring, 0);
		amdgpu_ring_write(ring, 1 << vmid); /* reference */
		amdgpu_ring_write(ring, 1 << vmid); /* mask */
		amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) \|
		SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
		}

		static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
		@@ -1589,7 +1575,9 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
		6 + /* sdma_v4_0_ring_emit_hdp_flush */
		3 + /* hdp invalidate */
		6 + /* sdma_v4_0_ring_emit_pipeline_sync */
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v4_0_ring_emit_vm_flush */
		/* sdma_v4_0_ring_emit_vm_flush */
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
		10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
		.emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
		.emit_ib = sdma_v4_0_ring_emit_ib,

drivers/gpu/drm/amd/amdgpu/soc15.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -28,6 +28,7 @@
		#include "nbio_v7_0.h"

		#define SOC15_FLUSH_GPU_TLB_NUM_WREG 4
		#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 1

		extern const struct amd_ip_funcs soc15_common_ip_funcs;

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

+6 −14

Original line number	Diff line number	Diff line
		@@ -1265,7 +1265,6 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
		uint64_t pd_addr)
		{
		struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
		unsigned eng = ring->vm_inv_eng;
		uint32_t data0, data1, mask;

		pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
		@@ -1275,12 +1274,6 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
		data1 = lower_32_bits(pd_addr);
		mask = 0xffffffff;
		uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);

		/* wait for flush */
		data0 = hub->vm_inv_eng0_ack + eng;
		data1 = 1 << vmid;
		mask = 1 << vmid;
		uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);
		}

		static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
		@@ -1313,17 +1306,12 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
		uint64_t pd_addr)
		{
		struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
		unsigned eng = ring->vm_inv_eng;

		pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);

		/* wait for reg writes */
		uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
		lower_32_bits(pd_addr), 0xffffffff);

		/* wait for flush */
		uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng,
		1 << vmid, 1 << vmid);
		}

		static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
		@@ -1669,7 +1657,9 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
		.set_wptr = uvd_v7_0_ring_set_wptr,
		.emit_frame_size =
		6 + 6 + /* hdp flush / invalidate */
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 16 + /* uvd_v7_0_ring_emit_vm_flush */
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
		8 + /* uvd_v7_0_ring_emit_vm_flush */
		14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
		.emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
		.emit_ib = uvd_v7_0_ring_emit_ib,
		@@ -1696,7 +1686,9 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
		.set_wptr = uvd_v7_0_enc_ring_set_wptr,
		.emit_frame_size =
		3 + 3 + /* hdp flush / invalidate */
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 8 + /* uvd_v7_0_enc_ring_emit_vm_flush */
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
		4 + /* uvd_v7_0_enc_ring_emit_vm_flush */
		5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
		1, /* uvd_v7_0_enc_ring_insert_end */
		.emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */

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