Commit f6ff3f6d authored by Xiaowei Bao's avatar Xiaowei Bao Committed by Shawn Guo
Browse files

arm64: dts: ls1028a: Add PCIe controller DT nodes 



LS1028a implements 2 PCIe 3.0 controllers.

Signed-off-by: default avatarXiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: default avatarHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Tested-by: default avatarMichael Walle <michael@walle.cc>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent ab43f030

arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

+54 −0
Original line number Diff line number Diff line
@@ -450,6 +450,60 @@ 
			status = "disabled";

		};



		pcie@3400000 {

			compatible = "fsl,ls1028a-pcie";

			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */

			       0x80 0x00000000 0x0 0x00002000>; /* configuration space */

			reg-names = "regs", "config";

			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */

				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */

			interrupt-names = "pme", "aer";

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			dma-coherent;

			num-viewport = <8>;

			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000   /* downstream I/O */

				  0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

			msi-parent = <&its>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;

			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */

			status = "disabled";

		};



		pcie@3500000 {

			compatible = "fsl,ls1028a-pcie";

			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */

			       0x88 0x00000000 0x0 0x00002000>; /* configuration space */

			reg-names = "regs", "config";

			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "pme", "aer";

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			dma-coherent;

			num-viewport = <8>;

			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000   /* downstream I/O */

				  0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

			msi-parent = <&its>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */

			status = "disabled";

		};



		smmu: iommu@5000000 {

			compatible = "arm,mmu-500";

			reg = <0 0x5000000 0 0x800000>;

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