Commit f6f64ed8 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Ulf Hansson
Browse files

clk: sunxi-ng: Add interface to query or configure MMC timing modes. 



Starting with the A83T SoC, Allwinner introduced a new timing mode for
its MMC clocks. The new mode changes how the MMC controller sample and
output clocks are delayed to match chip and board specifics. There are
two controls for this, one on the CCU side controlling how the clocks
behave, and one in the MMC controller controlling what inputs to take
and how to route them.

In the old mode, the MMC clock had 2 child clocks providing the output
and sample clocks, which could be delayed by a number of clock cycles
measured from the MMC clock's parent.

With the new mode, the 2 delay clocks are no longer active. Instead,
the delays and associated controls are moved into the MMC controller.
The output of the MMC clock is also halved.

The difference in how things are wired between the modes means that the
clock controls and the MMC controls must match. To achieve this in a
clear, explicit way, we introduce two functions for the MMC driver to
use: one queries the hardware for the current mode set, and the other
allows the MMC driver to request a mode.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent cd09780f

drivers/clk/sunxi-ng/Makefile

+1 −0
Original line number Diff line number Diff line 
# Common objects

lib-$(CONFIG_SUNXI_CCU)		+= ccu_common.o

lib-$(CONFIG_SUNXI_CCU)		+= ccu_mmc_timing.o

lib-$(CONFIG_SUNXI_CCU)		+= ccu_reset.o



# Base clock types

drivers/clk/sunxi-ng/ccu_common.h

+4 −0
Original line number Diff line number Diff line
@@ -23,6 +23,10 @@ 
#define CCU_FEATURE_FIXED_POSTDIV	BIT(3)

#define CCU_FEATURE_ALL_PREDIV		BIT(4)

#define CCU_FEATURE_LOCK_REG		BIT(5)

#define CCU_FEATURE_MMC_TIMING_SWITCH	BIT(6)



/* MMC timing mode switch bit */

#define CCU_MMC_NEW_TIMING_MODE		BIT(30)



struct device_node;

drivers/clk/sunxi-ng/ccu_mmc_timing.c

0 → 100644
+70 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and

 * may be copied, distributed, and modified under those terms.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <linux/clk-provider.h>

#include <linux/clk/sunxi-ng.h>



#include "ccu_common.h"



/**

 * sunxi_ccu_set_mmc_timing_mode: Configure the MMC clock timing mode

 * @clk: clock to be configured

 * @new_mode: true for new timing mode introduced in A83T and later

 *

 * Returns 0 on success, -ENOTSUPP if the clock does not support

 * switching modes.

 */

int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode)

{

	struct clk_hw *hw = __clk_get_hw(clk);

	struct ccu_common *cm = hw_to_ccu_common(hw);

	unsigned long flags;

	u32 val;



	if (!(cm->features & CCU_FEATURE_MMC_TIMING_SWITCH))

		return -ENOTSUPP;



	spin_lock_irqsave(cm->lock, flags);



	val = readl(cm->base + cm->reg);

	if (new_mode)

		val |= CCU_MMC_NEW_TIMING_MODE;

	else

		val &= ~CCU_MMC_NEW_TIMING_MODE;

	writel(val, cm->base + cm->reg);



	spin_unlock_irqrestore(cm->lock, flags);



	return 0;

}

EXPORT_SYMBOL_GPL(sunxi_ccu_set_mmc_timing_mode);



/**

 * sunxi_ccu_set_mmc_timing_mode: Get the current MMC clock timing mode

 * @clk: clock to query

 *

 * Returns 0 if the clock is in old timing mode, > 0 if it is in

 * new timing mode, and -ENOTSUPP if the clock does not support

 * this function.

 */

int sunxi_ccu_get_mmc_timing_mode(struct clk *clk)

{

	struct clk_hw *hw = __clk_get_hw(clk);

	struct ccu_common *cm = hw_to_ccu_common(hw);



	if (!(cm->features & CCU_FEATURE_MMC_TIMING_SWITCH))

		return -ENOTSUPP;



	return !!(readl(cm->base + cm->reg) & CCU_MMC_NEW_TIMING_MODE);

}

EXPORT_SYMBOL_GPL(sunxi_ccu_get_mmc_timing_mode);

include/linux/clk/sunxi-ng.h

0 → 100644
+35 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and

 * may be copied, distributed, and modified under those terms.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _LINUX_CLK_SUNXI_NG_H_

#define _LINUX_CLK_SUNXI_NG_H_



#include <linux/errno.h>



#ifdef CONFIG_SUNXI_CCU

int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode);

int sunxi_ccu_get_mmc_timing_mode(struct clk *clk);

#else

static inline int sunxi_ccu_set_mmc_timing_mode(struct clk *clk,

						bool new_mode)

{

	return -ENOTSUPP;

}



static inline int sunxi_ccu_get_mmc_timing_mode(struct clk *clk)

{

	return -ENOTSUPP;

}

#endif



#endif

CRA Git | Maintained and supported by SUSTech CRA and CCSE