Commit f6f52baf authored by Ingo Molnar's avatar Ingo Molnar
Browse files

x86: clean up esr_disable() methods



Impact: cleanup

Most subarchitectures want to disable the APIC ESR (Error Status Register),
because they generally have hardware hacks that wrap standard CPUs into
a bigger system and hence the APIC bus is quite non-standard and weirdnesses
(lockups) have been seen with ESR reporting.

Remove the esr_disable macros and put the desired flag into each
subarchitecture's genapic template directly.

Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent fe402e1f
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@@ -2,7 +2,6 @@
#define __ASM_MACH_APIC_H

#define xapic_phys_to_log_apicid(cpu) (per_cpu(x86_bios_cpu_apicid, cpu))
#define esr_disable (1)

static inline int bigsmp_apic_id_registered(void)
{
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@@ -4,7 +4,6 @@
#include <linux/gfp.h>

#define xapic_phys_to_log_apicid(cpu) per_cpu(x86_bios_cpu_apicid, cpu)
#define esr_disable (1)

static inline int es7000_apic_id_registered(void)
{
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@@ -18,7 +18,6 @@ static inline const struct cpumask *default_target_cpus(void)
} 

#define NO_BALANCE_IRQ (0)
#define esr_disable (0)

#ifdef CONFIG_X86_64
#include <asm/genapic.h>
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@@ -3,7 +3,6 @@

#include <asm/genapic.h>

#define esr_disable (apic->ESR_DISABLE)
#define NO_BALANCE_IRQ (apic->no_balance_irq)
#undef APIC_DEST_LOGICAL
#define APIC_DEST_LOGICAL (apic->apic_destination_logical)
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@@ -13,7 +13,6 @@ static inline const cpumask_t *numaq_target_cpus(void)
}

#define NO_BALANCE_IRQ (1)
#define esr_disable (1)

static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
{
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