Commit f6db7029 authored by Yunzhi Li's avatar Yunzhi Li Committed by Heiko Stuebner
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ARM: dts: rockchip: add rk3288 usb PHY 



This patch adds a device_node for RK3288 SoC usb phy. It also
defines the phy to be used by three usb controllers: usb_host0/1
and usb_otg.

Signed-off-by: default avatarYunzhi Li <lyz@rock-chips.com>
Tested-by: default avatarDoug Anderson <dianders@chromium.org>
Reviewed-by: default avatarDoug Anderson <dianders@chromium.org>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent c517d838

arch/arm/boot/dts/rk3288.dtsi

+35 −0
Original line number Diff line number Diff line
@@ -419,6 +419,8 @@ 
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_USBHOST0>;

		clock-names = "usbhost";

		phys = <&usbphy1>;

		phy-names = "usb";

		status = "disabled";

	};
@@ -431,6 +433,8 @@ 
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_USBHOST1>;

		clock-names = "otg";

		phys = <&usbphy2>;

		phy-names = "usb2-phy";

		status = "disabled";

	};
@@ -441,6 +445,8 @@ 
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_OTG0>;

		clock-names = "otg";

		phys = <&usbphy0>;

		phy-names = "usb2-phy";

		status = "disabled";

	};
@@ -697,6 +703,35 @@ 
		interrupts = <GIC_PPI 9 0xf04>;

	};



	usbphy: phy {

		compatible = "rockchip,rk3288-usb-phy";

		rockchip,grf = <&grf>;

		#address-cells = <1>;

		#size-cells = <0>;

		status = "disabled";



		usbphy0: usb-phy0 {

			#phy-cells = <0>;

			reg = <0x320>;

			clocks = <&cru SCLK_OTGPHY0>;

			clock-names = "phyclk";

		};



		usbphy1: usb-phy1 {

			#phy-cells = <0>;

			reg = <0x334>;

			clocks = <&cru SCLK_OTGPHY1>;

			clock-names = "phyclk";

		};



		usbphy2: usb-phy2 {

			#phy-cells = <0>;

			reg = <0x348>;

			clocks = <&cru SCLK_OTGPHY2>;

			clock-names = "phyclk";

		};

	};



	pinctrl: pinctrl {

		compatible = "rockchip,rk3288-pinctrl";

		rockchip,grf = <&grf>;

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