Commit f6c499ec authored by Daniel Vetter's avatar Daniel Vetter
Browse files

Merge tag 'gvt-next-2016-10-27' of https://github.com/01org/gvt-linux into drm-intel-next-queued 



gvt-next-2016-10-27

- Resolve current left build issue with ACPI=n and 32bit kernel
- TLB workaround from Arkadiusz
- vGPU reset fix from Ping
- workload scheduler nesting sleep fix from Changbin
- more misc fixes for sparse warnings and cleanups

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
parents 1c00164d e45d7b7f

drivers/gpu/drm/i915/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -87,6 +87,7 @@ config DRM_I915_USERPTR 
config DRM_I915_GVT

        bool "Enable Intel GVT-g graphics virtualization host support"

        depends on DRM_I915

        depends on 64BIT

        default n

        help

	  Choose this option if you want to enable Intel GVT-g graphics

drivers/gpu/drm/i915/gvt/cmd_parser.c

+14 −15
Original line number Diff line number Diff line
@@ -1145,7 +1145,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, 
		info->event = PRIMARY_B_FLIP_DONE;

		break;

	case MI_DISPLAY_FLIP_SKL_PLANE_1_C:

		info->pipe = PIPE_B;

		info->pipe = PIPE_C;

		info->event = PRIMARY_C_FLIP_DONE;

		break;

	default:
@@ -1201,20 +1201,19 @@ static int gen8_update_plane_mmio_from_mi_display_flip( 
	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;

	struct intel_vgpu *vgpu = s->vgpu;



#define write_bits(reg, e, s, v) do { \

	vgpu_vreg(vgpu, reg) &= ~GENMASK(e, s); \

	vgpu_vreg(vgpu, reg) |= (v << s); \

} while (0)



	write_bits(info->surf_reg, 31, 12, info->surf_val);

	if (IS_SKYLAKE(dev_priv))

		write_bits(info->stride_reg, 9, 0, info->stride_val);

	else

		write_bits(info->stride_reg, 15, 6, info->stride_val);

	write_bits(info->ctrl_reg, IS_SKYLAKE(dev_priv) ? 12 : 10,

		   10, info->tile_val);



#undef write_bits

	set_mask_bits(&vgpu_vreg(vgpu, info->surf_reg), GENMASK(31, 12),

		      info->surf_val << 12);

	if (IS_SKYLAKE(dev_priv)) {

		set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(9, 0),

			      info->stride_val);

		set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(12, 10),

			      info->tile_val << 10);

	} else {

		set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(15, 6),

			      info->stride_val << 6);

		set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(10, 10),

			      info->tile_val << 10);

	}



	vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;

	intel_vgpu_trigger_virtual_event(vgpu, info->event);

drivers/gpu/drm/i915/gvt/gtt.c

+2 −2
Original line number Diff line number Diff line
@@ -276,7 +276,7 @@ static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index) 
	pte = readq(addr);

#else

	pte = ioread32(addr);

	pte |= ioread32(addr + 4) << 32;

	pte |= (u64)ioread32(addr + 4) << 32;

#endif

	return pte;

}
@@ -1944,7 +1944,7 @@ static int create_scratch_page(struct intel_vgpu *vgpu) 
	mfn = intel_gvt_hypervisor_virt_to_mfn(vaddr);



	if (mfn == INTEL_GVT_INVALID_ADDR) {

		gvt_err("fail to translate vaddr:0x%llx\n", (u64)vaddr);

		gvt_err("fail to translate vaddr: 0x%p\n", vaddr);

		__free_page(gtt->scratch_page);

		gtt->scratch_page = NULL;

		return -ENXIO;

drivers/gpu/drm/i915/gvt/gvt.c

+6 −2
Original line number Diff line number Diff line
@@ -65,6 +65,8 @@ struct intel_gvt_io_emulation_ops intel_gvt_io_emulation_ops = { 
 */

int intel_gvt_init_host(void)

{

	int ret;



	if (intel_gvt_host.initialized)

		return 0;
@@ -90,7 +92,8 @@ int intel_gvt_init_host(void) 
		return -EINVAL;



	/* Try to detect if we're running in host instead of VM. */

	if (!intel_gvt_hypervisor_detect_host())

	ret = intel_gvt_hypervisor_detect_host();

	if (ret)

		return -ENODEV;



	gvt_dbg_core("Running with hypervisor %s in host mode\n",
@@ -103,19 +106,20 @@ int intel_gvt_init_host(void) 
static void init_device_info(struct intel_gvt *gvt)

{

	struct intel_gvt_device_info *info = &gvt->device_info;

	struct pci_dev *pdev = gvt->dev_priv->drm.pdev;



	if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {

		info->max_support_vgpus = 8;

		info->cfg_space_size = 256;

		info->mmio_size = 2 * 1024 * 1024;

		info->mmio_bar = 0;

		info->msi_cap_offset = IS_SKYLAKE(gvt->dev_priv) ? 0xac : 0x90;

		info->gtt_start_offset = 8 * 1024 * 1024;

		info->gtt_entry_size = 8;

		info->gtt_entry_size_shift = 3;

		info->gmadr_bytes_in_cmd = 8;

		info->max_surface_size = 36 * 1024 * 1024;

	}

	info->msi_cap_offset = pdev->msi_cap;

}



static int gvt_service_thread(void *data)

drivers/gpu/drm/i915/gvt/gvt.h

+2 −0
Original line number Diff line number Diff line
@@ -382,6 +382,8 @@ void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); 
int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa);



int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);

int setup_vgpu_mmio(struct intel_vgpu *vgpu);

void populate_pvinfo_page(struct intel_vgpu *vgpu);



#include "mpt.h"

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