Merge tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson into clk-next (f6b31309) · Commits · 戴 / test

drivers/clk/meson/gxbb.c

+58 −62

Original line number	Diff line number	Diff line
		@@ -278,20 +278,6 @@ static const struct pll_rate_table gxl_gp0_pll_rate_table[] = {
		{ /* sentinel */ },
		};

		static const struct clk_div_table cpu_div_table[] = {
		{ .val = 1, .div = 1 },
		{ .val = 2, .div = 2 },
		{ .val = 3, .div = 3 },
		{ .val = 2, .div = 4 },
		{ .val = 3, .div = 6 },
		{ .val = 4, .div = 8 },
		{ .val = 5, .div = 10 },
		{ .val = 6, .div = 12 },
		{ .val = 7, .div = 14 },
		{ .val = 8, .div = 16 },
		{ /* sentinel */ },
		};

		static struct meson_clk_pll gxbb_fixed_pll = {
		.m = {
		.reg_off = HHI_MPLL_CNTL,
		@@ -612,21 +598,10 @@ static struct meson_clk_mpll gxbb_mpll2 = {
		};

		/*
		* FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
		* post-dividers and should be modeled with their respective PLLs via the
		* forthcoming coordinated clock rates feature
		* FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers
		* and should be modeled with their respective PLLs via the forthcoming
		* coordinated clock rates feature
		*/
		static struct meson_clk_cpu gxbb_cpu_clk = {
		.reg_off = HHI_SYS_CPU_CLK_CNTL1,
		.div_table = cpu_div_table,
		.clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
		.hw.init = &(struct clk_init_data){
		.name = "cpu_clk",
		.ops = &meson_clk_cpu_ops,
		.parent_names = (const char *[]){ "sys_pll" },
		.num_parents = 1,
		},
		};

		static u32 mux_table_clk81[] = { 6, 5, 7 };

		@@ -676,7 +651,7 @@ static struct clk_gate gxbb_clk81 = {
		.ops = &clk_gate_ops,
		.parent_names = (const char *[]){ "mpeg_clk_div" },
		.num_parents = 1,
		.flags = (CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED \| CLK_IS_CRITICAL),
		.flags = (CLK_SET_RATE_PARENT \| CLK_IS_CRITICAL),
		},
		};

		@@ -951,6 +926,51 @@ static struct clk_mux gxbb_cts_i958 = {
		},
		};

		static struct clk_divider gxbb_32k_clk_div = {
		.reg = (void *)HHI_32K_CLK_CNTL,
		.shift = 0,
		.width = 14,
		.lock = &clk_lock,
		.hw.init = &(struct clk_init_data){
		.name = "32k_clk_div",
		.ops = &clk_divider_ops,
		.parent_names = (const char *[]){ "32k_clk_sel" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_DIVIDER_ROUND_CLOSEST,
		},
		};

		static struct clk_gate gxbb_32k_clk = {
		.reg = (void *)HHI_32K_CLK_CNTL,
		.bit_idx = 15,
		.lock = &clk_lock,
		.hw.init = &(struct clk_init_data){
		.name = "32k_clk",
		.ops = &clk_gate_ops,
		.parent_names = (const char *[]){ "32k_clk_div" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		},
		};

		static const char *gxbb_32k_clk_parent_names[] = {
		"xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
		};

		static struct clk_mux gxbb_32k_clk_sel = {
		.reg = (void *)HHI_32K_CLK_CNTL,
		.mask = 0x3,
		.shift = 16,
		.lock = &clk_lock,
		.hw.init = &(struct clk_init_data){
		.name = "32k_clk_sel",
		.ops = &clk_mux_ops,
		.parent_names = gxbb_32k_clk_parent_names,
		.num_parents = 4,
		.flags = CLK_SET_RATE_PARENT,
		},
		};

		/* Everything Else (EE) domain gates */
		static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
		static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
		@@ -1045,7 +1065,6 @@ static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
		static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
		.hws = {
		[CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
		[CLKID_CPUCLK] = &gxbb_cpu_clk.hw,
		[CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
		[CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
		[CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
		@@ -1158,6 +1177,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
		[CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
		[CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
		[CLKID_CTS_I958] = &gxbb_cts_i958.hw,
		[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
		[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
		[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
		},
		.num = NR_CLKS,
		};
		@@ -1165,7 +1187,6 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
		static struct clk_hw_onecell_data gxl_hw_onecell_data = {
		.hws = {
		[CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
		[CLKID_CPUCLK] = &gxbb_cpu_clk.hw,
		[CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
		[CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
		[CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
		@@ -1278,6 +1299,9 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
		[CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
		[CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
		[CLKID_CTS_I958] = &gxbb_cts_i958.hw,
		[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
		[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
		[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
		},
		.num = NR_CLKS,
		};
		@@ -1392,6 +1416,7 @@ static struct clk_gate *const gxbb_clk_gates[] = {
		&gxbb_mali_1,
		&gxbb_cts_amclk,
		&gxbb_cts_mclk_i958,
		&gxbb_32k_clk,
		};

		static struct clk_mux *const gxbb_clk_muxes[] = {
		@@ -1403,6 +1428,7 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
		&gxbb_cts_amclk_sel,
		&gxbb_cts_mclk_i958_sel,
		&gxbb_cts_i958,
		&gxbb_32k_clk_sel,
		};

		static struct clk_divider *const gxbb_clk_dividers[] = {
		@@ -1411,6 +1437,7 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
		&gxbb_mali_0_div,
		&gxbb_mali_1_div,
		&gxbb_cts_mclk_i958_div,
		&gxbb_32k_clk_div,
		};

		static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
		@@ -1430,7 +1457,6 @@ struct clkc_data {
		unsigned int clk_dividers_count;
		struct meson_clk_audio_divider const clk_audio_dividers;
		unsigned int clk_audio_dividers_count;
		struct meson_clk_cpu *cpu_clk;
		struct clk_hw_onecell_data *hw_onecell_data;
		};

		@@ -1447,7 +1473,6 @@ static const struct clkc_data gxbb_clkc_data = {
		.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
		.clk_audio_dividers = gxbb_audio_dividers,
		.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
		.cpu_clk = &gxbb_cpu_clk,
		.hw_onecell_data = &gxbb_hw_onecell_data,
		};

		@@ -1464,7 +1489,6 @@ static const struct clkc_data gxl_clkc_data = {
		.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
		.clk_audio_dividers = gxbb_audio_dividers,
		.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
		.cpu_clk = &gxbb_cpu_clk,
		.hw_onecell_data = &gxl_hw_onecell_data,
		};

		@@ -1479,8 +1503,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
		const struct clkc_data *clkc_data;
		void __iomem *clk_base;
		int ret, clkid, i;
		struct clk_hw *parent_hw;
		struct clk *parent_clk;
		struct device *dev = &pdev->dev;

		clkc_data = of_device_get_match_data(&pdev->dev);
		@@ -1502,9 +1524,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
		for (i = 0; i < clkc_data->clk_mplls_count; i++)
		clkc_data->clk_mplls[i]->base = clk_base;

		/* Populate the base address for CPU clk */
		clkc_data->cpu_clk->base = clk_base;

		/* Populate base address for gates */
		for (i = 0; i < clkc_data->clk_gates_count; i++)
		clkc_data->clk_gates[i]->reg = clk_base +
		@@ -1538,29 +1557,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
		goto iounmap;
		}

		/*
		* Register CPU clk notifier
		*
		* FIXME this is wrong for a lot of reasons. First, the muxes should be
		* struct clk_hw objects. Second, we shouldn't program the muxes in
		* notifier handlers. The tricky programming sequence will be handled
		* by the forthcoming coordinated clock rates mechanism once that
		* feature is released.
		*
		* Furthermore, looking up the parent this way is terrible. At some
		* point we will stop allocating a default struct clk when registering
		* a new clk_hw, and this hack will no longer work. Releasing the ccr
		* feature before that time solves the problem :-)
		*/
		parent_hw = clk_hw_get_parent(&clkc_data->cpu_clk->hw);
		parent_clk = parent_hw->clk;
		ret = clk_notifier_register(parent_clk, &clkc_data->cpu_clk->clk_nb);
		if (ret) {
		pr_err("%s: failed to register clock notifier for cpu_clk\n",
		__func__);
		goto iounmap;
		}

		return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
		clkc_data->hw_onecell_data);

drivers/clk/meson/gxbb.h

+14 −11

Original line number	Diff line number	Diff line
		@@ -171,7 +171,7 @@
		* to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h
		*/
		#define CLKID_SYS_PLL 0
		/* CLKID_CPUCLK */
		/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
		/* CLKID_HDMI_PLL */
		#define CLKID_FIXED_PLL 3
		/* CLKID_FCLK_DIV2 */
		@@ -191,12 +191,12 @@
		#define CLKID_ISA 18
		#define CLKID_PL301 19
		#define CLKID_PERIPHS 20
		#define CLKID_SPICC 21
		/* CLKID_SPICC */
		/* CLKID_I2C */
		/* #define CLKID_SAR_ADC */
		#define CLKID_SMART_CARD 24
		/* CLKID_RNG0 */
		#define CLKID_UART0 26
		/* CLKID_UART0 */
		#define CLKID_SDHC 27
		#define CLKID_STREAM 28
		#define CLKID_ASYNC_FIFO 29
		@@ -209,7 +209,7 @@
		/* CLKID_ETH */
		#define CLKID_DEMUX 37
		/* CLKID_AIU_GLUE */
		#define CLKID_IEC958 39
		/* CLKID_IEC958 */
		/* CLKID_I2S_OUT */
		#define CLKID_AMCLK 41
		#define CLKID_AIFIFO2 42
		@@ -218,7 +218,7 @@
		#define CLKID_ADC 45
		#define CLKID_BLKMV 46
		/* CLKID_AIU */
		#define CLKID_UART1 48
		/* CLKID_UART1 */
		#define CLKID_G2D 49
		/* CLKID_USB0 */
		/* CLKID_USB1 */
		@@ -238,7 +238,7 @@
		/* CLKID_USB0_DDR_BRIDGE */
		#define CLKID_MMC_PCLK 66
		#define CLKID_DVIN 67
		#define CLKID_UART2 68
		/* CLKID_UART2 */
		/* #define CLKID_SANA */
		#define CLKID_VPU_INTR 70
		#define CLKID_SEC_AHB_AHB3_BRIDGE 71
		@@ -251,7 +251,7 @@
		#define CLKID_GCLK_VENCI_INT 78
		#define CLKID_DAC_CLK 79
		/* CLKID_AOCLK_GATE */
		#define CLKID_IEC958_GATE 81
		/* CLKID_IEC958_GATE */
		#define CLKID_ENC480P 82
		#define CLKID_RNG1 83
		#define CLKID_GCLK_VENCI_INT1 84
		@@ -277,15 +277,18 @@
		#define CLKID_MALI_1_DIV 104
		/* CLKID_MALI_1 */
		/* CLKID_MALI */
		#define CLKID_CTS_AMCLK 107
		/* CLKID_CTS_AMCLK */
		#define CLKID_CTS_AMCLK_SEL 108
		#define CLKID_CTS_AMCLK_DIV 109
		#define CLKID_CTS_MCLK_I958 110
		/* CLKID_CTS_MCLK_I958 */
		#define CLKID_CTS_MCLK_I958_SEL 111
		#define CLKID_CTS_MCLK_I958_DIV 112
		#define CLKID_CTS_I958 113
		/* CLKID_CTS_I958 */
		#define CLKID_32K_CLK 114
		#define CLKID_32K_CLK_SEL 115
		#define CLKID_32K_CLK_DIV 116

		#define NR_CLKS 114
		#define NR_CLKS 117

		/* include the CLKIDs that have been made part of the stable DT binding */
		#include <dt-bindings/clock/gxbb-clkc.h>

drivers/clk/meson/meson8b.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -399,7 +399,7 @@ struct clk_gate meson8b_clk81 = {
		.ops = &clk_gate_ops,
		.parent_names = (const char *[]){ "mpeg_clk_div" },
		.num_parents = 1,
		.flags = (CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED),
		.flags = (CLK_SET_RATE_PARENT \| CLK_IS_CRITICAL),
		},
		};

include/dt-bindings/clock/gxbb-clkc.h

+9 −1

Original line number	Diff line number	Diff line
		@@ -5,7 +5,6 @@
		#ifndef __GXBB_CLKC_H
		#define __GXBB_CLKC_H

		#define CLKID_CPUCLK 1
		#define CLKID_HDMI_PLL 2
		#define CLKID_FCLK_DIV2 4
		#define CLKID_FCLK_DIV3 5
		@@ -13,24 +12,30 @@
		#define CLKID_GP0_PLL 9
		#define CLKID_CLK81 12
		#define CLKID_MPLL2 15
		#define CLKID_SPICC 21
		#define CLKID_I2C 22
		#define CLKID_SAR_ADC 23
		#define CLKID_RNG0 25
		#define CLKID_UART0 26
		#define CLKID_SPI 34
		#define CLKID_ETH 36
		#define CLKID_AIU_GLUE 38
		#define CLKID_IEC958 39
		#define CLKID_I2S_OUT 40
		#define CLKID_MIXER_IFACE 44
		#define CLKID_AIU 47
		#define CLKID_UART1 48
		#define CLKID_USB0 50
		#define CLKID_USB1 51
		#define CLKID_USB 55
		#define CLKID_HDMI_PCLK 63
		#define CLKID_USB1_DDR_BRIDGE 64
		#define CLKID_USB0_DDR_BRIDGE 65
		#define CLKID_UART2 68
		#define CLKID_SANA 69
		#define CLKID_GCLK_VENCI_INT0 77
		#define CLKID_AOCLK_GATE 80
		#define CLKID_IEC958_GATE 81
		#define CLKID_AO_I2C 93
		#define CLKID_SD_EMMC_A 94
		#define CLKID_SD_EMMC_B 95
		@@ -42,5 +47,8 @@
		#define CLKID_MALI_1_SEL 103
		#define CLKID_MALI_1 105
		#define CLKID_MALI 106
		#define CLKID_CTS_AMCLK 107
		#define CLKID_CTS_MCLK_I958 110
		#define CLKID_CTS_I958 113

		#endif /* __GXBB_CLKC_H */

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