Merge tag 'pinctrl-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microsemi/Microchip Serial GPIO controller

maintainers:

  - Lars Povlsen <lars.povlsen@microchip.com>

description: |

  By using a serial interface, the SIO controller significantly extend

  the number of available GPIOs with a minimum number of additional

  pins on the device. The primary purpose of the SIO controllers is to

  connect control signals from SFP modules and to act as an LED

  controller.

properties:

  $nodename:

    pattern: "^gpio@[0-9a-f]+$"

  compatible:

    enum:

      - microchip,sparx5-sgpio

      - mscc,ocelot-sgpio

      - mscc,luton-sgpio

  "#address-cells":

    const: 1

  "#size-cells":

    const: 0

  reg:

    maxItems: 1

  clocks:

    maxItems: 1

  microchip,sgpio-port-ranges:

    description: This is a sequence of tuples, defining intervals of

      enabled ports in the serial input stream. The enabled ports must

      match the hardware configuration in order for signals to be

      properly written/read to/from the controller holding

      registers. Being tuples, then number of arguments must be

      even. The tuples mast be ordered (low, high) and are

      inclusive.

    $ref: /schemas/types.yaml#/definitions/uint32-matrix

    items:

      items:

        - description: |

            "low" indicates start bit number of range

          minimum: 0

          maximum: 31

        - description: |

            "high" indicates end bit number of range

          minimum: 0

          maximum: 31

    minItems: 1

    maxItems: 32

  bus-frequency:

    description: The sgpio controller frequency (Hz). This dictates

      the serial bitstream speed, which again affects the latency in

      getting control signals back and forth between external shift

      registers. The speed must be no larger than half the system

      clock, and larger than zero.

    default: 12500000

patternProperties:

  "^gpio@[0-1]$":

    type: object

    properties:

      compatible:

        const: microchip,sparx5-sgpio-bank

      reg:

        description: |

          The GPIO bank number. "0" is designates the input pin bank,

          "1" the output bank.

        maxItems: 1

      gpio-controller: true

      '#gpio-cells':

        description: |

         Specifies the pin (port and bit) and flags. Note that the

         SGIO pin is defined by *2* numbers, a port number between 0

         and 31, and a bit index, 0 to 3. The maximum bit number is

         controlled indirectly by the "ngpios" property: (ngpios/32).

        const: 3

      interrupts:

        description: Specifies the sgpio IRQ (in parent controller)

        maxItems: 1

      interrupt-controller: true

      '#interrupt-cells':

        description:

         Specifies the pin (port and bit) and flags, as defined in

         defined in include/dt-bindings/interrupt-controller/irq.h

        const: 3

      ngpios:

        description: The numbers of GPIO's exposed. This must be a

          multiple of 32.

        minimum: 32

        maximum: 128

    required:

      - compatible

      - reg

      - gpio-controller

      - '#gpio-cells'

      - ngpios

    additionalProperties: false

additionalProperties: false

required:

  - compatible

  - reg

  - clocks

  - microchip,sgpio-port-ranges

  - "#address-cells"

  - "#size-cells"

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    sgpio2: gpio@1101059c {

      #address-cells = <1>;

      #size-cells = <0>;

      compatible = "microchip,sparx5-sgpio";

      clocks = <&sys_clk>;

      pinctrl-0 = <&sgpio2_pins>;

      pinctrl-names = "default";

      reg = <0x1101059c 0x100>;

      microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;

      bus-frequency = <25000000>;

      sgpio_in2: gpio@0 {

        reg = <0>;

        compatible = "microchip,sparx5-sgpio-bank";

        gpio-controller;

        #gpio-cells = <3>;

        ngpios = <96>;

        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-controller;

        #interrupt-cells = <3>;

      };

      sgpio_out2: gpio@1 {

        compatible = "microchip,sparx5-sgpio-bank";

        reg = <1>;

        gpio-controller;

        #gpio-cells = <3>;

        ngpios = <96>;

      };

    };

Required properties:

 - compatible		: Should be "mscc,ocelot-pinctrl",

			  "mscc,jaguar2-pinctrl" or "microchip,sparx5-pinctrl"

			  "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",

			  "mscc,luton-pinctrl" or "mscc,serval-pinctrl"

 - reg			: Address and length of the register set for the device

 - gpio-controller	: Indicates this device is a GPIO controller

 - #gpio-cells		: Must be 2.

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)

  Low Power Island (LPI) TLMM block

maintainers:

  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description: |

  This binding describes the Top Level Mode Multiplexer block found in the

  LPASS LPI IP on most Qualcomm SoCs

properties:

  compatible:

    const: qcom,sm8250-lpass-lpi-pinctrl

  reg:

    minItems: 2

    maxItems: 2

  clocks:

    items:

      - description: LPASS Core voting clock

      - description: LPASS Audio voting clock

  clock-names:

    items:

      - const: core

      - const: audio

  gpio-controller: true

  '#gpio-cells':

    description: Specifying the pin number and flags, as defined in

      include/dt-bindings/gpio/gpio.h

    const: 2

  gpio-ranges:

    maxItems: 1

#PIN CONFIGURATION NODES

patternProperties:

  '-pins$':

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.

    $ref: "/schemas/pinctrl/pincfg-node.yaml"

    properties:

      pins:

        description:

          List of gpio pins affected by the properties specified in this

          subnode.

        items:

          oneOf:

            - pattern: "^gpio([0-9]|[1-9][0-9])$"

        minItems: 1

        maxItems: 14

      function:

        enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,

                qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,

                dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,

                i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,

                dmic3_data, i2s2_data ]

        description:

          Specify the alternative function to be configured for the specified

          pins.

      drive-strength:

        enum: [2, 4, 6, 8, 10, 12, 14, 16]

        default: 2

        description:

          Selects the drive strength for the specified pins, in mA.

      slew-rate:

        enum: [0, 1, 2, 3]

        default: 0

        description: |

            0: No adjustments

            1: Higher Slew rate (faster edges)

            2: Lower Slew rate (slower edges)

            3: Reserved (No adjustments)

      bias-pull-down: true

      bias-pull-up: true

      bias-disable: true

      output-high: true

      output-low: true

    required:

      - pins

      - function

    additionalProperties: false

required:

  - compatible

  - reg

  - clocks

  - clock-names

  - gpio-controller

  - '#gpio-cells'

  - gpio-ranges

additionalProperties: false

examples:

  - |

    #include <dt-bindings/sound/qcom,q6afe.h>

    lpi_tlmm: pinctrl@33c0000 {

        compatible = "qcom,sm8250-lpass-lpi-pinctrl";

        reg = <0x33c0000 0x20000>,

              <0x3550000 0x10000>;

        clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

        clock-names = "core", "audio";

        gpio-controller;

        #gpio-cells = <2>;

        gpio-ranges = <&lpi_tlmm 0 0 14>;

    };

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/qcom,msm8953-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. MSM8953 TLMM block

maintainers:

  - Bjorn Andersson <bjorn.andersson@linaro.org>

description: |

  This binding describes the Top Level Mode Multiplexer block found in the

  MSM8953 platform.

properties:

  compatible:

    const: qcom,msm8953-pinctrl

  reg:

    maxItems: 1

  interrupts:

    description: Specifies the TLMM summary IRQ

    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':

    description:

      Specifies the PIN numbers and Flags, as defined in defined in

      include/dt-bindings/interrupt-controller/irq.h

    const: 2

  gpio-controller: true

  '#gpio-cells':

    description: Specifying the pin number and flags, as defined in

      include/dt-bindings/gpio/gpio.h

    const: 2

  gpio-ranges:

    maxItems: 1

#PIN CONFIGURATION NODES

patternProperties:

  '-pins$':

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.

    $ref: "/schemas/pinctrl/pincfg-node.yaml"

    properties:

      pins:

        description:

          List of gpio pins affected by the properties specified in this

          subnode.

        items:

          oneOf:

            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"

            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,

                      sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0,

                      qdsd_data1, qdsd_data2, qdsd_data3 ]

        minItems: 1

        maxItems: 16

      function:

        description:

          Specify the alternative function to be configured for the specified

          pins.

        enum: [ accel_int, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1,

                atest_char, atest_char0, atest_char1, atest_char2, atest_char3,

                atest_gpsadc_dtest0_native, atest_gpsadc_dtest1_native, atest_tsens,

                atest_wlan0, atest_wlan1, bimc_dte0, bimc_dte1, blsp1_spi,

                blsp3_spi, blsp6_spi, blsp7_spi, blsp_i2c1, blsp_i2c2, blsp_i2c3,

                blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_spi1,

                blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7,

                blsp_spi8, blsp_uart2, blsp_uart4, blsp_uart5, blsp_uart6, cam0_ldo,

                cam1_ldo, cam1_rst, cam1_standby, cam2_rst, cam2_standby, cam3_rst,

                cam3_standby, cam_irq, cam_mclk, cap_int, cci_async, cci_i2c,

                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,

                cdc_pdm0, codec_int1, codec_int2, codec_reset, cri_trng, cri_trng0,

                cri_trng1, dac_calib0, dac_calib1, dac_calib10, dac_calib11,

                dac_calib12, dac_calib13, dac_calib14, dac_calib15, dac_calib16,

                dac_calib17, dac_calib18, dac_calib19, dac_calib2, dac_calib20,

                dac_calib21, dac_calib22, dac_calib23, dac_calib24, dac_calib25,

                dac_calib3, dac_calib4, dac_calib5, dac_calib6, dac_calib7,

                dac_calib8, dac_calib9, dbg_out, ddr_bist, dmic0_clk, dmic0_data,

                ebi_cdc, ebi_ch0, ext_lpass, flash_strobe, fp_int, gcc_gp1_clk_a,

                gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a,

                gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gpio, gsm0_tx, gsm1_tx,

                gyro_int, hall_int, hdmi_int, key_focus, key_home, key_snapshot,

                key_volp, ldo_en, ldo_update, lpass_slimbus, lpass_slimbus0,

                lpass_slimbus1, m_voc, mag_int, mdp_vsync, mipi_dsi0, modem_tsync,

                mss_lte, nav_pps, nav_pps_in_a, nav_pps_in_b, nav_tsync,

                nfc_disable, nfc_dwl, nfc_irq, ois_sync, pa_indicator, pbs0, pbs1,

                pbs2, pressure_int, pri_mi2s, pri_mi2s_mclk_a, pri_mi2s_mclk_b,

                pri_mi2s_ws, prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b,

                pwr_down, pwr_modem_enabled_a, pwr_modem_enabled_b,

                pwr_nav_enabled_a, pwr_nav_enabled_b, qdss_cti_trig_in_a0,

                qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,

                qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,

                qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,

                qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,

                qdss_tracedata_b, sd_write, sdcard_det, sec_mi2s, sec_mi2s_mclk_a,

                sec_mi2s_mclk_b, smb_int, ss_switch, ssbi_wtr1, ts_resout,

                ts_sample, ts_xvdd, tsens_max, uim1_clk, uim1_data, uim1_present,

                uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,

                uim_batt, us_emitter, us_euro, wcss_bt, wcss_fm, wcss_wlan,

                wcss_wlan0, wcss_wlan1, wcss_wlan2, wsa_en, wsa_io, wsa_irq ]

      drive-strength:

        enum: [2, 4, 6, 8, 10, 12, 14, 16]

        default: 2

        description:

          Selects the drive strength for the specified pins, in mA.

      bias-pull-down: true

      bias-pull-up: true

      bias-disable: true

      output-high: true

      output-low: true

    required:

      - pins

      - function

    additionalProperties: false

required:

  - compatible

  - reg

  - interrupts

  - interrupt-controller

  - '#interrupt-cells'

  - gpio-controller

  - '#gpio-cells'

  - gpio-ranges

additionalProperties: false

examples:

  - |

        #include <dt-bindings/interrupt-controller/arm-gic.h>

        tlmm: pinctrl@1000000 {

              compatible = "qcom,msm8953-pinctrl";

              reg = <0x01000000 0x300000>;

              interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

              interrupt-controller;

              #interrupt-cells = <2>;

              gpio-controller;

              #gpio-cells = <2>;

              gpio-ranges = <&tlmm 0 0 142>;

              serial_default: serial-pins {

                    pins = "gpio4", "gpio5";

                    function = "blsp_uart2";

                    drive-strength = <2>;

                    bias-disable;

              };

        };

		    "qcom,pm8150b-gpio"

		    "qcom,pm6150-gpio"

		    "qcom,pm6150l-gpio"

		    "qcom,pmx55-gpio"

		    And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"

		    if the device is on an spmi bus or an ssbi bus respectively

		    gpio1-gpio12 for pm8150l (hole on gpio7)

		    gpio1-gpio10 for pm6150

		    gpio1-gpio12 for pm6150l

		    gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10

					    and gpio11)

- function:

	Usage: required