Commit f66a4976 authored by Eli Billauer's avatar Eli Billauer Committed by Greg Kroah-Hartman
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staging: xillybus: Removed mmiowb() before mutex_unlock()



The relevant sequences consist of two I/O memory writes. The second write
depends on the first one. mmiowb() was inserted to make sure that no other
thread inserts a "first write" before the current one finished its second.

As a mutex protects this critical sequence, mmiowb() is unnecessary.

Signed-off-by: default avatarEli Billauer <eli.billauer@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a5b2e028
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+0 −4
Original line number Diff line number Diff line
@@ -908,8 +908,6 @@ static ssize_t xillybus_read(struct file *filp, char __user *userbuf,
					   channel->endpoint->registers +
					   fpga_buf_ctrl_reg);

				mmiowb(); /* Just to appear safe */

				mutex_unlock(&channel->endpoint->
					     register_mutex);
			}
@@ -1118,7 +1116,6 @@ static int xillybus_myflush(struct xilly_channel *channel, long timeout)
			   (2 << 24) |  /* Opcode 2, submit buffer */
			   (bufidx << 12),
			   channel->endpoint->registers + fpga_buf_ctrl_reg);
		mmiowb(); /* Just to appear safe */

		mutex_unlock(&channel->endpoint->register_mutex);
	} else if (bufidx == 0)
@@ -1369,7 +1366,6 @@ static ssize_t xillybus_write(struct file *filp, const char __user *userbuf,
					   (bufidx << 12),
					   channel->endpoint->registers +
					   fpga_buf_ctrl_reg);
				mmiowb(); /* Just to appear safe */

				mutex_unlock(&channel->endpoint->
					     register_mutex);