Merge tag 'drivers-3.12' of git://git.infradead.org/linux-mvebu into next/soc (f668adeb) · Commits · 戴 / test

Documentation/devicetree/bindings/bus/mvebu-mbus.txt

0 → 100644

+276 −0

Original line number	Diff line number	Diff line

		* Marvell MBus

		Required properties:

		- compatible: Should be set to one of the following:
		marvell,armada370-mbus
		marvell,armadaxp-mbus
		marvell,armada370-mbus
		marvell,armadaxp-mbus
		marvell,kirkwood-mbus
		marvell,dove-mbus
		marvell,orion5x-88f5281-mbus
		marvell,orion5x-88f5182-mbus
		marvell,orion5x-88f5181-mbus
		marvell,orion5x-88f6183-mbus
		marvell,mv78xx0-mbus

		- address-cells: Must be '2'. The first cell for the MBus ID encoding,
		the second cell for the address offset within the window.

		- size-cells: Must be '1'.

		- ranges: Must be set up to provide a proper translation for each child.
		See the examples below.

		- controller: Contains a single phandle referring to the MBus controller
		node. This allows to specify the node that contains the
		registers that control the MBus, which is typically contained
		within the internal register window (see below).

		Optional properties:

		- pcie-mem-aperture: This optional property contains the aperture for
		the memory region of the PCIe driver.
		If it's defined, it must encode the base address and
		size for the address decoding windows allocated for
		the PCIe memory region.

		- pcie-io-aperture: Just as explained for the above property, this
		optional property contains the aperture for the
		I/O region of the PCIe driver.

		* Marvell MBus controller

		Required properties:

		- compatible: Should be set to "marvell,mbus-controller".

		- reg: Device's register space.
		Two entries are expected (see the examples below):
		the first one controls the devices decoding window and
		the second one controls the SDRAM decoding window.

		Example:

		soc {
		compatible = "marvell,armada370-mbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		pcie-mem-aperture = <0xe0000000 0x8000000>;
		pcie-io-aperture = <0xe8000000 0x100000>;

		internal-regs {
		compatible = "simple-bus";

		mbusc: mbus-controller@20000 {
		compatible = "marvell,mbus-controller";
		reg = <0x20000 0x100>, <0x20180 0x20>;
		};

		/* more children ...*/
		};
		};

		** MBus address decoding window specification

		The MBus children address space is comprised of two cells: the first one for
		the window ID and the second one for the offset within the window.
		In order to allow to describe valid and non-valid window entries, the
		following encoding is used:

		0xSIAA0000 0x00oooooo

		Where:

		S = 0x0 for a MBus valid window
		S = 0xf for a non-valid window (see below)

		If S = 0x0, then:

		I = 4-bit window target ID
		AA = windpw attribute

		If S = 0xf, then:

		I = don't care
		AA = 1 for internal register

		Following the above encoding, for each ranges entry for a MBus valid window
		(S = 0x0), an address decoding window is allocated. On the other side,
		entries for translation that do not correspond to valid windows (S = 0xf)
		are skipped.

		soc {
		compatible = "marvell,armada370-mbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;

		ranges = <0xf0010000 0 0 0xd0000000 0x100000
		0x01e00000 0 0 0xfff00000 0x100000>;

		bootrom {
		compatible = "marvell,bootrom";
		reg = <0x01e00000 0 0x100000>;
		};

		/* other children */
		...

		internal-regs {
		compatible = "simple-bus";
		ranges = <0 0xf0010000 0 0x100000>;

		mbusc: mbus-controller@20000 {
		compatible = "marvell,mbus-controller";
		reg = <0x20000 0x100>, <0x20180 0x20>;
		};

		/* more children ...*/
		};
		};

		In the shown example, the translation entry in the 'ranges' property is what
		makes the MBus driver create a static decoding window for the corresponding
		given child device. Note that the binding does not require child nodes to be
		present. Of course, child nodes are needed to probe the devices.

		Since each window is identified by its target ID and attribute ID there's
		a special macro that can be use to simplify the translation entries:

		#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))

		Using this macro, the above example would be:

		soc {
		compatible = "marvell,armada370-mbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;

		ranges = < MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
		MBUS_ID(0x01, 0xe0) 0 0 0xfff00000 0x100000>;

		bootrom {
		compatible = "marvell,bootrom";
		reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
		};

		/* other children */
		...

		internal-regs {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

		mbusc: mbus-controller@20000 {
		compatible = "marvell,mbus-controller";
		reg = <0x20000 0x100>, <0x20180 0x20>;
		};

		/* other children */
		...
		};
		};


		** About the window base address

		Remember the MBus controller allows a great deal of flexibility for choosing
		the decoding window base address. When planning the device tree layout it's
		possible to choose any address as the base address, provided of course there's
		a region large enough available, and with the required alignment.

		Yet in other words: there's nothing preventing us from setting a base address
		of 0xf0000000, or 0xd0000000 for the NOR device shown above, if such region is
		unused.

		** Window allocation policy

		The mbus-node ranges property defines a set of mbus windows that are expected
		to be set by the operating system and that are guaranteed to be free of overlaps
		with one another or with the system memory ranges.

		Each entry in the property refers to exactly one window. If the operating system
		choses to use a different set of mbus windows, it must ensure that any address
		translations performed from downstream devices are adapted accordingly.

		The operating system may insert additional mbus windows that do not conflict
		with the ones listed in the ranges, e.g. for mapping PCIe devices.
		As a special case, the internal register window must be set up by the boot
		loader at the address listed in the ranges property, since access to that region
		is needed to set up the other windows.

		** Example

		See the example below, where a more complete device tree is shown:

		soc {
		compatible = "marvell,armadaxp-mbus", "simple-bus";
		controller = <&mbusc>;

		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 /* internal-regs */
		MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
		MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;

		bootrom {
		compatible = "marvell,bootrom";
		reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
		};

		devbus-bootcs {
		status = "okay";
		ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;

		/* NOR */
		nor {
		compatible = "cfi-flash";
		reg = <0 0x8000000>;
		bank-width = <2>;
		};
		};

		pcie-controller {
		compatible = "marvell,armada-xp-pcie";
		status = "okay";
		device_type = "pci";

		#address-cells = <3>;
		#size-cells = <2>;

		ranges =
		<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
		0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
		0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
		0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
		0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
		0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
		0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;


		pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
		};
		};

		internal-regs {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

		mbusc: mbus-controller@20000 {
		reg = <0x20000 0x100>, <0x20180 0x20>;
		};

		interrupt-controller@20000 {
		reg = <0x20a00 0x2d0>, <0x21070 0x58>;
		};
		};
		};

Documentation/devicetree/bindings/pci/mvebu-pci.txt

+109 −36

Original line number	Diff line number	Diff line
		* Marvell EBU PCIe interfaces

		Mandatory properties:

		- compatible: one of the following values:
		marvell,armada-370-pcie
		marvell,armada-xp-pcie
		@@ -10,11 +11,49 @@ Mandatory properties:
		- #interrupt-cells, set to <1>
		- bus-range: PCI bus numbers covered
		- device_type, set to "pci"
		- ranges: ranges for the PCI memory and I/O regions, as well as the
		MMIO registers to control the PCIe interfaces.
		- ranges: ranges describing the MMIO registers to control the PCIe
		interfaces, and ranges describing the MBus windows needed to access
		the memory and I/O regions of each PCIe interface.

		The ranges describing the MMIO registers have the following layout:

		0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s

		where:

		* r is a 32-bits value that gives the offset of the MMIO
		registers of this PCIe interface, from the base of the internal
		registers.

		* s is a 32-bits value that give the size of this MMIO
		registers area. This range entry translates the '0x82000000 0 r' PCI
		address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
		of the internal register window (as identified by MBUS_ID(0xf0,
		0x01)).

		The ranges describing the MBus windows have the following layout:

		0x8t000000 s 0 MBUS_ID(w, a) 0 1 0

		where:

		* t is the type of the MBus window (as defined by the standard PCI DT
		bindings), 1 for I/O and 2 for memory.

		In addition, the Device Tree node must have sub-nodes describing each
		* s is the PCI slot that corresponds to this PCIe interface

		* w is the 'target ID' value for the MBus window

		* a the 'attribute' value for the MBus window.

		Since the location and size of the different MBus windows is not fixed in
		hardware, and only determined in runtime, those ranges cover the full first
		4 GB of the physical address space, and do not translate into a valid CPU
		address.

		In addition, the device tree node must have sub-nodes describing each
		PCIe interface, having the following mandatory properties:

		- reg: used only for interrupt mapping, so only the first four bytes
		are used to refer to the correct bus number and device number.
		- assigned-addresses: reference to the MMIO registers used to control
		@@ -26,7 +65,8 @@ PCIe interface, having the following mandatory properties:
		- #address-cells, set to <3>
		- #size-cells, set to <2>
		- #interrupt-cells, set to <1>
		- ranges, empty property.
		- ranges, translating the MBus windows ranges of the parent node into
		standard PCI addresses.
		- interrupt-map-mask and interrupt-map, standard PCI properties to
		define the mapping of the PCIe interface to interrupt numbers.

		@@ -47,27 +87,50 @@ pcie-controller {

		bus-range = <0x00 0xff>;

		ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
		0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
		0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
		0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
		0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
		0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
		0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
		0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
		0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
		0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
		0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
		0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
		ranges =
		<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
		0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
		0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
		0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
		0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
		0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
		0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
		0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
		0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
		0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
		0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
		0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
		0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
		0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
		0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
		0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
		0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
		0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */

		0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
		0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
		0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
		0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
		0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
		0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
		0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
		0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */

		0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
		0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */

		0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
		0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;

		pcie@1,0 {
		device_type = "pci";
		assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
		assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
		reg = <0x0800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges;
		ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
		0x81000000 0 0 0x81000000 0x1 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 58>;
		marvell,pcie-port = <0>;
		@@ -78,12 +141,13 @@ pcie-controller {

		pcie@2,0 {
		device_type = "pci";
		assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
		assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
		reg = <0x1000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges;
		ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
		0x81000000 0 0 0x81000000 0x2 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 59>;
		marvell,pcie-port = <0>;
		@@ -94,12 +158,13 @@ pcie-controller {

		pcie@3,0 {
		device_type = "pci";
		assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
		assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
		reg = <0x1800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges;
		ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
		0x81000000 0 0 0x81000000 0x3 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 60>;
		marvell,pcie-port = <0>;
		@@ -110,12 +175,13 @@ pcie-controller {

		pcie@4,0 {
		device_type = "pci";
		assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
		assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
		reg = <0x2000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges;
		ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
		0x81000000 0 0 0x81000000 0x4 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 61>;
		marvell,pcie-port = <0>;
		@@ -126,12 +192,13 @@ pcie-controller {

		pcie@5,0 {
		device_type = "pci";
		assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
		assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
		reg = <0x2800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges;
		ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
		0x81000000 0 0 0x81000000 0x5 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 62>;
		marvell,pcie-port = <1>;
		@@ -142,12 +209,13 @@ pcie-controller {

		pcie@6,0 {
		device_type = "pci";
		assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
		assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
		reg = <0x3000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges;
		ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
		0x81000000 0 0 0x81000000 0x6 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 63>;
		marvell,pcie-port = <1>;
		@@ -158,12 +226,13 @@ pcie-controller {

		pcie@7,0 {
		device_type = "pci";
		assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
		assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
		reg = <0x3800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges;
		ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
		0x81000000 0 0 0x81000000 0x7 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 64>;
		marvell,pcie-port = <1>;
		@@ -174,12 +243,13 @@ pcie-controller {

		pcie@8,0 {
		device_type = "pci";
		assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
		assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
		reg = <0x4000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges;
		ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
		0x81000000 0 0 0x81000000 0x8 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 65>;
		marvell,pcie-port = <1>;
		@@ -187,14 +257,16 @@ pcie-controller {
		clocks = <&gateclk 12>;
		status = "disabled";
		};

		pcie@9,0 {
		device_type = "pci";
		assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
		assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
		reg = <0x4800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges;
		ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
		0x81000000 0 0 0x81000000 0x9 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 99>;
		marvell,pcie-port = <2>;
		@@ -205,12 +277,13 @@ pcie-controller {

		pcie@10,0 {
		device_type = "pci";
		assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
		assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
		reg = <0x5000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges;
		ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
		0x81000000 0 0 0x81000000 0xa 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 103>;
		marvell,pcie-port = <3>;

arch/arm/boot/dts/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
		dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
		armada-370-mirabox.dtb \
		armada-370-rd.dtb \
		armada-xp-axpwifiap.dtb \
		armada-xp-db.dtb \
		armada-xp-gp.dtb \
		armada-xp-openblocks-ax3-4.dtb

arch/arm/boot/dts/armada-370-db.dts

+4 −1

Original line number	Diff line number	Diff line
		@@ -14,7 +14,7 @@
		*/

		/dts-v1/;
		/include/ "armada-370.dtsi"
		#include "armada-370.dtsi"

		/ {
		model = "Marvell Armada 370 Evaluation Board";
		@@ -30,6 +30,9 @@
		};

		soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
		MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;

		internal-regs {
		serial@12000 {
		clock-frequency = <200000000>;

arch/arm/boot/dts/armada-370-mirabox.dts

+20 −17

Original line number	Diff line number	Diff line
		@@ -9,7 +9,7 @@
		*/

		/dts-v1/;
		/include/ "armada-370.dtsi"
		#include "armada-370.dtsi"

		/ {
		model = "Globalscale Mirabox";
		@@ -25,6 +25,25 @@
		};

		soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
		MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;

		pcie-controller {
		status = "okay";

		/* Internal mini-PCIe connector */
		pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
		};

		/* Connected on the PCB to a USB 3.0 XHCI controller */
		pcie@2,0 {
		/* Port 1, Lane 0 */
		status = "okay";
		};
		};

		internal-regs {
		serial@12000 {
		clock-frequency = <200000000>;
		@@ -120,22 +139,6 @@
		reg = <0x25>;
		};
		};

		pcie-controller {
		status = "okay";

		/* Internal mini-PCIe connector */
		pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
		};

		/* Connected on the PCB to a USB 3.0 XHCI controller */
		pcie@2,0 {
		/* Port 1, Lane 0 */
		status = "okay";
		};
		};
		};
		};
		};

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