Commit f639c497 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/fifo_underrun: use intel_de_*() functions for register access 



The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().

Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().

No functional changes.

Generated using the following semantic patch:

@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)

@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)

@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)

Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/fca7d63b3aa669b5984be45b5968f47fb0b64b2b.1579871655.git.jani.nikula@intel.com
parent aa93f4fd

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

+20 −17
Original line number Diff line number Diff line
@@ -95,12 +95,12 @@ static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) 


	lockdep_assert_held(&dev_priv->irq_lock);



	if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)

	if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)

		return;



	enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);

	I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);

	POSTING_READ(reg);

	intel_de_write(dev_priv, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);

	intel_de_posting_read(dev_priv, reg);



	trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);

	DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
@@ -118,10 +118,11 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, 
	if (enable) {

		u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);



		I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);

		POSTING_READ(reg);

		intel_de_write(dev_priv, reg,

			       enable_mask | PIPE_FIFO_UNDERRUN_STATUS);

		intel_de_posting_read(dev_priv, reg);

	} else {

		if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS)

		if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS)

			DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));

	}

}
@@ -143,15 +144,15 @@ static void ivb_check_fifo_underruns(struct intel_crtc *crtc) 
{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	u32 err_int = I915_READ(GEN7_ERR_INT);

	u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT);



	lockdep_assert_held(&dev_priv->irq_lock);



	if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)

		return;



	I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));

	POSTING_READ(GEN7_ERR_INT);

	intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));

	intel_de_posting_read(dev_priv, GEN7_ERR_INT);



	trace_intel_cpu_fifo_underrun(dev_priv, pipe);

	DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe));
@@ -163,7 +164,8 @@ static void ivb_set_fifo_underrun_reporting(struct drm_device *dev, 
{

	struct drm_i915_private *dev_priv = to_i915(dev);

	if (enable) {

		I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));

		intel_de_write(dev_priv, GEN7_ERR_INT,

			       ERR_INT_FIFO_UNDERRUN(pipe));



		if (!ivb_can_enable_err_int(dev))

			return;
@@ -173,7 +175,7 @@ static void ivb_set_fifo_underrun_reporting(struct drm_device *dev, 
		ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);



		if (old &&

		    I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {

		    intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {

			DRM_ERROR("uncleared fifo underrun on pipe %c\n",

				  pipe_name(pipe));

		}
@@ -209,15 +211,16 @@ static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) 
{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pch_transcoder = crtc->pipe;

	u32 serr_int = I915_READ(SERR_INT);

	u32 serr_int = intel_de_read(dev_priv, SERR_INT);



	lockdep_assert_held(&dev_priv->irq_lock);



	if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0)

		return;



	I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));

	POSTING_READ(SERR_INT);

	intel_de_write(dev_priv, SERR_INT,

		       SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));

	intel_de_posting_read(dev_priv, SERR_INT);



	trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);

	DRM_ERROR("pch fifo underrun on pch transcoder %c\n",
@@ -231,7 +234,7 @@ static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, 
	struct drm_i915_private *dev_priv = to_i915(dev);



	if (enable) {

		I915_WRITE(SERR_INT,

		intel_de_write(dev_priv, SERR_INT,

			       SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));



		if (!cpt_can_enable_serr_int(dev))
@@ -241,7 +244,7 @@ static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, 
	} else {

		ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);



		if (old && I915_READ(SERR_INT) &

		if (old && intel_de_read(dev_priv, SERR_INT) &

		    SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {

			DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",

				  pipe_name(pch_transcoder));

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