Commit f62e3162 authored by Guo Ren's avatar Guo Ren
Browse files

csky: Support dynamic start physical address 



Before this patch csky-linux need CONFIG_RAM_BASE to determine start
physical address. Now we use phys_offset variable to replace the macro
of PHYS_OFFSET and we setup phys_offset with real physical address which
is determined during startup in head.S.

With this patch we needn't re-compile kernel for different start
physical address. ie: 0x0 / 0xc0000000 start physical address could use
the same vmlinux, be care different start address must be 512MB aligned.

Signed-off-by: default avatarGuo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
parent bf241682

arch/csky/abiv1/inc/abi/ckmmu.h

+20 −0
Original line number Diff line number Diff line
@@ -40,6 +40,26 @@ static inline void write_mmu_entryhi(int value) 
	cpwcr("cpcr4", value);

}



static inline unsigned long read_mmu_msa0(void)

{

	return cprcr("cpcr30");

}



static inline void write_mmu_msa0(unsigned long value)

{

	cpwcr("cpcr30", value);

}



static inline unsigned long read_mmu_msa1(void)

{

	return cprcr("cpcr31");

}



static inline void write_mmu_msa1(unsigned long value)

{

	cpwcr("cpcr31", value);

}



/*

 * TLB operations.

 */

arch/csky/abiv1/inc/abi/entry.h

+17 −2
Original line number Diff line number Diff line
@@ -144,9 +144,24 @@ 
.endm



.macro SETUP_MMU rx

	lrw	\rx, PHYS_OFFSET | 0xe

	/* Select MMU as co-processor */

	cpseti	cp15



	/*

	 * cpcr30 format:

	 * 31 - 29 | 28 - 4 | 3 | 2 | 1 | 0

	 *   BA     Reserved  C   D   V

	 */

	cprcr	\rx, cpcr30

	lsri	\rx, 28

	lsli	\rx, 28

	addi	\rx, 0xe

	cpwcr	\rx, cpcr30

	lrw	\rx, (PHYS_OFFSET + 0x20000000) | 0xe



	lsri	\rx, 28

	addi	\rx, 2

	lsli	\rx, 28

	addi	\rx, 0xe

	cpwcr	\rx, cpcr31

.endm

arch/csky/abiv2/inc/abi/ckmmu.h

+20 −0
Original line number Diff line number Diff line
@@ -42,6 +42,26 @@ static inline void write_mmu_entryhi(int value) 
	mtcr("cr<4, 15>", value);

}



static inline unsigned long read_mmu_msa0(void)

{

	return mfcr("cr<30, 15>");

}



static inline void write_mmu_msa0(unsigned long value)

{

	mtcr("cr<30, 15>", value);

}



static inline unsigned long read_mmu_msa1(void)

{

	return mfcr("cr<31, 15>");

}



static inline void write_mmu_msa1(unsigned long value)

{

	mtcr("cr<31, 15>", value);

}



/*

 * TLB operations.

 */

arch/csky/abiv2/inc/abi/entry.h

+22 −2
Original line number Diff line number Diff line
@@ -163,9 +163,29 @@ 
.endm



.macro SETUP_MMU rx

	lrw	\rx, PHYS_OFFSET | 0xe

	/* Check MMU on | off */

	mfcr	\rx, cr18

	btsti	\rx, 0

	bt	1f

	grs	\rx, 1f

	br	2f

1:

	/*

	 * cr<30, 15> format:

	 * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

	 *   BA     Reserved  SH  WA  B   SO SEC  C   D   V

	 */

	mfcr	\rx, cr<30, 15>

2:

	lsri	\rx, 28

	lsli	\rx, 28

	addi	\rx, 0x1ce

	mtcr	\rx, cr<30, 15>

	lrw	\rx, (PHYS_OFFSET + 0x20000000) | 0xe



	lsri	\rx, 28

	addi	\rx, 2

	lsli	\rx, 28

	addi	\rx, 0x1ce

	mtcr	\rx, cr<31, 15>

.endm

arch/csky/include/asm/mmu_context.h

+2 −2
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 
static inline void tlbmiss_handler_setup_pgd(unsigned long pgd, bool kernel)

{

	pgd -= PAGE_OFFSET;

	pgd += PHYS_OFFSET;

	pgd += phys_offset;

	pgd |= 1;

	setup_pgd(pgd, kernel);

}
@@ -29,7 +29,7 @@ static inline void tlbmiss_handler_setup_pgd(unsigned long pgd, bool kernel) 


static inline unsigned long tlb_get_pgd(void)

{

	return ((get_pgd() - PHYS_OFFSET) & ~1) + PAGE_OFFSET;

	return ((get_pgd() - phys_offset) & ~1) + PAGE_OFFSET;

}



#define cpu_context(cpu, mm)	((mm)->context.asid[cpu])

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