Commit f6081a73 authored by Niklas Cassel's avatar Niklas Cassel Committed by Viresh Kumar
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dt-bindings: opp: qcom-nvmem: Support pstates provided by a power domain 



Some Qualcomm SoCs have support for Core Power Reduction (CPR).
On these platforms, we need to attach to the power domain provider
providing the performance states, so that the leaky device (the CPU)
can configure the performance states (which represent different
CPU clock frequencies).

Signed-off-by: default avatarNiklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
parent a4099060

Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt

+112 −1
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ operating-points-v2 table when it is parsed by the OPP framework. 


Required properties:

--------------------

In 'cpus' nodes:

In 'cpu' nodes:

- operating-points-v2: Phandle to the operating-points-v2 table to use.



In 'operating-points-v2' table:
@@ -23,6 +23,15 @@ In 'operating-points-v2' table: 


Optional properties:

--------------------

In 'cpu' nodes:

- power-domains: A phandle pointing to the PM domain specifier which provides

		the performance states available for active state management.

		Please refer to the power-domains bindings

		Documentation/devicetree/bindings/power/power_domain.txt

		and also examples below.

- power-domain-names: Should be

	- 'cpr' for qcs404.



In 'operating-points-v2' table:

- nvmem-cells: A phandle pointing to a nvmem-cells node representing the

		efuse registers that has information about the
@@ -682,3 +691,105 @@ soc { 
		};

	};

};



Example 2:

---------



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		CPU0: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x100>;

			....

			clocks = <&apcs_glb>;

			operating-points-v2 = <&cpu_opp_table>;

			power-domains = <&cpr>;

			power-domain-names = "cpr";

		};



		CPU1: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x101>;

			....

			clocks = <&apcs_glb>;

			operating-points-v2 = <&cpu_opp_table>;

			power-domains = <&cpr>;

			power-domain-names = "cpr";

		};



		CPU2: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x102>;

			....

			clocks = <&apcs_glb>;

			operating-points-v2 = <&cpu_opp_table>;

			power-domains = <&cpr>;

			power-domain-names = "cpr";

		};



		CPU3: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x103>;

			....

			clocks = <&apcs_glb>;

			operating-points-v2 = <&cpu_opp_table>;

			power-domains = <&cpr>;

			power-domain-names = "cpr";

		};

	};



	cpu_opp_table: cpu-opp-table {

		compatible = "operating-points-v2-kryo-cpu";

		opp-shared;



		opp-1094400000 {

			opp-hz = /bits/ 64 <1094400000>;

			required-opps = <&cpr_opp1>;

		};

		opp-1248000000 {

			opp-hz = /bits/ 64 <1248000000>;

			required-opps = <&cpr_opp2>;

		};

		opp-1401600000 {

			opp-hz = /bits/ 64 <1401600000>;

			required-opps = <&cpr_opp3>;

		};

	};



	cpr_opp_table: cpr-opp-table {

		compatible = "operating-points-v2-qcom-level";



		cpr_opp1: opp1 {

			opp-level = <1>;

			qcom,opp-fuse-level = <1>;

		};

		cpr_opp2: opp2 {

			opp-level = <2>;

			qcom,opp-fuse-level = <2>;

		};

		cpr_opp3: opp3 {

			opp-level = <3>;

			qcom,opp-fuse-level = <3>;

		};

	};



....



soc {

....

	cpr: power-controller@b018000 {

		compatible = "qcom,qcs404-cpr", "qcom,cpr";

		reg = <0x0b018000 0x1000>;

		....

		vdd-apc-supply = <&pms405_s3>;

		#power-domain-cells = <0>;

		operating-points-v2 = <&cpr_opp_table>;

		....

	};

};

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