ARM: cti: fix manipulation of debug lock registers (f600b9fc) · Commits · 戴 / test

The LOCKSTATUS register for memory-mapped coresight devices indicates whether or not the device in question implements hardware locking. If not, locking is not present (i.e. LSR.SLI == 0) and LAR is write-ignore, so software doesn't actually need to check the status register at all. This patch removes the broken LSR checks. Cc: Ming Lei <ming.lei@canonical.com> Reported-by:

Mike Williams <michael.williams@arm.com> Signed-off-by:

Will Deacon <will.deacon@arm.com>

arch/arm/include/asm/cti.h

+2 −18

Original line number	Diff line number	Diff line
		@@ -146,15 +146,7 @@ static inline void cti_irq_ack(struct cti *cti)
		*/
		static inline void cti_unlock(struct cti *cti)
		{
		void __iomem *base = cti->base;
		unsigned long val;

		val = __raw_readl(base + LOCKSTATUS);

		if (val & 1) {
		val = LOCKCODE;
		__raw_writel(val, base + LOCKACCESS);
		}
		__raw_writel(LOCKCODE, cti->base + LOCKACCESS);
		}

		/**
		@@ -166,14 +158,6 @@ static inline void cti_unlock(struct cti *cti)
		*/
		static inline void cti_lock(struct cti *cti)
		{
		void __iomem *base = cti->base;
		unsigned long val;

		val = __raw_readl(base + LOCKSTATUS);

		if (!(val & 1)) {
		val = ~LOCKCODE;
		__raw_writel(val, base + LOCKACCESS);
		}
		__raw_writel(~LOCKCODE, cti->base + LOCKACCESS);
		}
		#endif

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