Commit f5f857f4 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: disable cg pg task when pp uninitialize.



fix bug on uvd pg enabled, when reboot vm in pass through case,
we need to notify smu power up uvd/vce if they were power down.
otherwise, the vbios post will fail.

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8201a67a
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+1 −1
Original line number Diff line number Diff line
@@ -154,7 +154,7 @@ int pem_task_powerdown_vce_tasks(struct pp_eventmgr *eventmgr, struct pem_event_

int pem_task_disable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
{
	/* TODO */
	phm_disable_clock_power_gatings(eventmgr->hwmgr);
	return 0;
}

+13 −0
Original line number Diff line number Diff line
@@ -209,6 +209,19 @@ int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
	return 0;
}

int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface)) {
		if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
			return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
	}
	return 0;
}


int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
{
	PHM_FUNC_CHECK(hwmgr);
+1 −0
Original line number Diff line number Diff line
@@ -334,6 +334,7 @@ struct phm_clocks {
	uint32_t clock[MAX_NUM_CLOCKS];
};

extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);