Commit f5d9b7f0 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon/dpm: fix r600_enable_sclk_control() 



Actually program the correct register to enable
engine clock scaling control.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f4f85a8c

drivers/gpu/drm/radeon/r600_dpm.c

+2 −2
Original line number Diff line number Diff line
@@ -278,9 +278,9 @@ bool r600_dynamicpm_enabled(struct radeon_device *rdev) 
void r600_enable_sclk_control(struct radeon_device *rdev, bool enable)

{

	if (enable)

		WREG32_P(GENERAL_PWRMGT, 0, ~SCLK_PWRMGT_OFF);

		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);

	else

		WREG32_P(GENERAL_PWRMGT, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);

		WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);

}



void r600_enable_mclk_control(struct radeon_device *rdev, bool enable)

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