i2c: owl: Clear NACK and BUS error bits (f5b3f433) · Commits · 戴 / test

When the NACK and BUS error bits are set by the hardware, the driver is responsible for clearing them by writing "1" into the corresponding status registers. Hence perform the necessary operations in owl_i2c_interrupt(). Fixes: ("i2c: Add Actions Semiconductor Owl family S900 I2C driver") Reported-by:

Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:

Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Signed-off-by:

Wolfram Sang <wsa@kernel.org>

drivers/i2c/busses/i2c-owl.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -176,6 +176,9 @@ static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
		fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT);
		if (fifostat & OWL_I2C_FIFOSTAT_RNB) {
		i2c_dev->err = -ENXIO;
		/* Clear NACK error bit by writing "1" */
		owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOSTAT,
		OWL_I2C_FIFOSTAT_RNB, true);
		goto stop;
		}

		@@ -183,6 +186,9 @@ static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
		stat = readl(i2c_dev->base + OWL_I2C_REG_STAT);
		if (stat & OWL_I2C_STAT_BEB) {
		i2c_dev->err = -EIO;
		/* Clear BUS error bit by writing "1" */
		owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
		OWL_I2C_STAT_BEB, true);
		goto stop;
		}

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