Commit f58cdf7e authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Will Deacon
Browse files

arm64: capabilities: Merge duplicate Cavium erratum entries 



Merge duplicate entries for a single capability using the midr
range list for Cavium errata 30115 and 27456.

Cc: Andrew Pinski <apinski@cavium.com>
Cc: David Daney <david.daney@cavium.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: default avatarVladimir Murzin <vladimir.murzin@arm.com>
Tested-by: default avatarVladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent c9460dcb

arch/arm64/include/asm/cputype.h

+1 −0
Original line number Diff line number Diff line
@@ -152,6 +152,7 @@ struct midr_range { 
	}



#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)

#define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)

#define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)



static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)

arch/arm64/kernel/cpu_errata.c

+24 −26
Original line number Diff line number Diff line
@@ -570,6 +570,28 @@ static const struct midr_range arm64_harden_el2_vectors[] = { 


#endif



#ifdef CONFIG_CAVIUM_ERRATUM_27456

static const struct midr_range cavium_erratum_27456_cpus[] = {

	/* Cavium ThunderX, T88 pass 1.x - 2.1 */

	MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),

	/* Cavium ThunderX, T81 pass 1.0 */

	MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),

	{},

};

#endif



#ifdef CONFIG_CAVIUM_ERRATUM_30115

static const struct midr_range cavium_erratum_30115_cpus[] = {

	/* Cavium ThunderX, T88 pass 1.x - 2.2 */

	MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),

	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */

	MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),

	/* Cavium ThunderX, T83 pass 1.0 */

	MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),

	{},

};

#endif



#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE

static const struct midr_range workaround_clean_cache[] = {

#if	defined(CONFIG_ARM64_ERRATUM_826319) || \
@@ -642,40 +664,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
#endif

#ifdef CONFIG_CAVIUM_ERRATUM_27456

	{

	/* Cavium ThunderX, T88 pass 1.x - 2.1 */

		.desc = "Cavium erratum 27456",

		.capability = ARM64_WORKAROUND_CAVIUM_27456,

		ERRATA_MIDR_RANGE(MIDR_THUNDERX,

				  0, 0,

				  1, 1),

	},

	{

	/* Cavium ThunderX, T81 pass 1.0 */

		.desc = "Cavium erratum 27456",

		.capability = ARM64_WORKAROUND_CAVIUM_27456,

		ERRATA_MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),

		ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),

	},

#endif

#ifdef CONFIG_CAVIUM_ERRATUM_30115

	{

	/* Cavium ThunderX, T88 pass 1.x - 2.2 */

		.desc = "Cavium erratum 30115",

		.capability = ARM64_WORKAROUND_CAVIUM_30115,

		ERRATA_MIDR_RANGE(MIDR_THUNDERX,

				      0, 0,

				      1, 2),

	},

	{

	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */

		.desc = "Cavium erratum 30115",

		.capability = ARM64_WORKAROUND_CAVIUM_30115,

		ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),

	},

	{

	/* Cavium ThunderX, T83 pass 1.0 */

		.desc = "Cavium erratum 30115",

		.capability = ARM64_WORKAROUND_CAVIUM_30115,

		ERRATA_MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),

		ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),

	},

#endif

	{

CRA Git | Maintained and supported by SUSTech CRA and CCSE