Commit f5786b8e authored by Philipp Zabel's avatar Philipp Zabel Committed by Shawn Guo
Browse files

ARM i.MX53: Fix UART pad configuration 



The current default pad configuration for UART RX and TX pads sets a 360k
pull-down and writes 1 to a reserved bit (1 << 0). It doesn't seem right to
me that in idle state, the UART has to keep the signal high against a
pull-down resistor.

This patch instead sets a 100k pull-up, which incidentally corresponds to the
register reset value for all but one (MX53_PAD_KEY_ROW0__UART4_RXD_MUX) pad,
and removes the write to the reserved bit.

Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent ad81f054

arch/arm/boot/dts/imx53.dtsi

+16 −16
Original line number Diff line number Diff line
@@ -725,15 +725,15 @@ 
				uart1 {

					pinctrl_uart1_1: uart1grp-1 {

						fsl,pins = <

							MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5

							MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5

							MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4

							MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4

						>;

					};



					pinctrl_uart1_2: uart1grp-2 {

						fsl,pins = <

							MX53_PAD_PATA_DIOW__UART1_TXD_MUX  0x1c5

							MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5

							MX53_PAD_PATA_DIOW__UART1_TXD_MUX  0x1e4

							MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4

						>;

					};
@@ -748,8 +748,8 @@ 
				uart2 {

					pinctrl_uart2_1: uart2grp-1 {

						fsl,pins = <

							MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5

							MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     0x1c5

							MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4

							MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     0x1e4

						>;

					};
@@ -766,17 +766,17 @@ 
				uart3 {

					pinctrl_uart3_1: uart3grp-1 {

						fsl,pins = <

							MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5

							MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5

							MX53_PAD_PATA_DA_1__UART3_CTS	  0x1c5

							MX53_PAD_PATA_DA_2__UART3_RTS	  0x1c5

							MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4

							MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4

							MX53_PAD_PATA_DA_1__UART3_CTS	  0x1e4

							MX53_PAD_PATA_DA_2__UART3_RTS	  0x1e4

						>;

					};



					pinctrl_uart3_2: uart3grp-2 {

						fsl,pins = <

							MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5

							MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5

							MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4

							MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4

						>;

					};
@@ -785,8 +785,8 @@ 
				uart4 {

					pinctrl_uart4_1: uart4grp-1 {

						fsl,pins = <

							MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5

							MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5

							MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4

							MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4

						>;

					};

				};
@@ -794,8 +794,8 @@ 
				uart5 {

					pinctrl_uart5_1: uart5grp-1 {

						fsl,pins = <

							MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5

							MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5

							MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4

							MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4

						>;

					};

				};

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