Commit f568dd7f authored by Uwe Kleine-König's avatar Uwe Kleine-König
Browse files

imx/mach-mx3: use constants namespaced by the corresponding SOC (easy part) 



This just leaves cpu.c, devices.c and mm.c to clean up.  As these files
are used on more than one SOC they need some more work.

Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Alberto Panizzo <maramaopercheseimorto@gmail.com>
Cc: Valentin Longchamp <valentin.longchamp@epfl.ch>
Cc: Daniel Mack <daniel@caiaq.de>
Cc: Guennadi Liakhovetski <lg@denx.de>
Cc: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Magnus Lilja <lilja.magnus@gmail.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Harro Haan <hrhaan@yahoo.com>
Cc: Jean Delvare <khali@linux-fr.org>
Cc: Luotao Fu <l.fu@pengutronix.de>
Cc: Ilya Yanok <yanok@emcraft.com>
parent 3f35d1f5

arch/arm/mach-mx3/armadillo5x0.c

+6 −6
Original line number Diff line number Diff line
@@ -182,8 +182,8 @@ static struct physmap_flash_data armadillo5x0_nor_flash_pdata = { 


static struct resource armadillo5x0_nor_flash_resource = {

	.flags		= IORESOURCE_MEM,

	.start		= CS0_BASE_ADDR,

	.end		= CS0_BASE_ADDR + SZ_64M - 1,

	.start		= MX31_CS0_BASE_ADDR,

	.end		= MX31_CS0_BASE_ADDR + SZ_64M - 1,

};



static struct platform_device armadillo5x0_nor_flash = {
@@ -311,8 +311,8 @@ static struct imxmmc_platform_data sdhc_pdata = { 
 */

static struct resource armadillo5x0_smc911x_resources[] = {

	{

		.start	= CS3_BASE_ADDR,

		.end	= CS3_BASE_ADDR + SZ_32M - 1,

		.start	= MX31_CS3_BASE_ADDR,

		.end	= MX31_CS3_BASE_ADDR + SZ_32M - 1,

		.flags	= IORESOURCE_MEM,

	}, {

		.start	= IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
@@ -406,8 +406,8 @@ static struct sys_timer armadillo5x0_timer = { 


MACHINE_START(ARMADILLO5X0, "Armadillo-500")

	/* Maintainer: Alberto Panizzo  */

	.phys_io	= AIPS1_BASE_ADDR,

	.io_pg_offst	= ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,

	.phys_io	= MX31_AIPS1_BASE_ADDR,

	.io_pg_offst	= ((MX31_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,

	.boot_params	= PHYS_OFFSET + 0x00000100,

	.map_io		= mx31_map_io,

	.init_irq	= mx31_init_irq,

arch/arm/mach-mx3/clock-imx35.c

+2 −2
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ 
#include <mach/hardware.h>

#include <mach/common.h>



#define CCM_BASE	IO_ADDRESS(CCM_BASE_ADDR)

#define CCM_BASE	IO_ADDRESS(MX35_CCM_BASE_ADDR)



#define CCM_CCMR        0x00

#define CCM_PDR0        0x04
@@ -504,7 +504,7 @@ int __init mx35_clocks_init() 
	__raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);

	__raw_writel(0, CCM_BASE + CCM_CGR3);



	mxc_timer_init(&gpt_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT);

	mxc_timer_init(&gpt_clk, IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);



	return 0;

}

arch/arm/mach-mx3/clock.c

+2 −2
Original line number Diff line number Diff line
@@ -618,14 +618,14 @@ int __init mx31_clocks_init(unsigned long fref) 


	mx31_read_cpu_rev();



	if (mx31_revision() >= CHIP_REV_2_0) {

	if (mx31_revision() >= MX31_CHIP_REV_2_0) {

		reg = __raw_readl(MXC_CCM_PMCR1);

		/* No PLL restart on DVFS switch; enable auto EMI handshake */

		reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;

		__raw_writel(reg, MXC_CCM_PMCR1);

	}



	mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT);

	mxc_timer_init(&ipg_clk, IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT);



	return 0;

}

arch/arm/mach-mx3/crm_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ 
#define CKIH_CLK_FREQ_27MHZ     27000000

#define CKIL_CLK_FREQ           32768



#define MXC_CCM_BASE		IO_ADDRESS(CCM_BASE_ADDR)

#define MXC_CCM_BASE		IO_ADDRESS(MX31_CCM_BASE_ADDR)



/* Register addresses */

#define MXC_CCM_CCMR		(MXC_CCM_BASE + 0x00)

arch/arm/mach-mx3/iomux.c

+1 −1
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 
/*

 * IOMUX register (base) addresses

 */

#define IOMUX_BASE	IO_ADDRESS(IOMUXC_BASE_ADDR)

#define IOMUX_BASE	IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)

#define IOMUXINT_OBS1	(IOMUX_BASE + 0x000)

#define IOMUXINT_OBS2	(IOMUX_BASE + 0x004)

#define IOMUXGPR	(IOMUX_BASE + 0x008)

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