usb: mtu3: reinitialize CSR registers (f55df11e) · Commits · 戴 / test

drivers/usb/mtu3/mtu3_core.c

+32 −29

Original line number	Diff line number	Diff line
		@@ -202,6 +202,36 @@ static void mtu3_intr_enable(struct mtu3 *mtu)
		mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
		}

		static void mtu3_set_speed(struct mtu3 *mtu);

		/* CSR registers will be reset to default value if port is disabled */
		static void mtu3_csr_init(struct mtu3 *mtu)
		{
		void __iomem *mbase = mtu->mac_base;

		if (mtu->is_u3_ip) {
		/* disable LGO_U1/U2 by default */
		mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
		SW_U1_REQUEST_ENABLE \| SW_U2_REQUEST_ENABLE);
		/* enable accept LGO_U1/U2 link command from host */
		mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
		SW_U1_ACCEPT_ENABLE \| SW_U2_ACCEPT_ENABLE);
		/* device responses to u3_exit from host automatically */
		mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
		/* automatically build U2 link when U3 detect fail */
		mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
		/* auto clear SOFT_CONN when clear USB3_EN if work as HS */
		mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
		}

		mtu3_set_speed(mtu);

		/* delay about 0.1us from detecting reset to send chirp-K */
		mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
		/* enable automatical HWRW from L1 */
		mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE);
		}

		/* reset: u2 - data toggle, u3 - SeqN, flow control status etc */
		static void mtu3_ep_reset(struct mtu3_ep *mep)
		{
		@@ -267,13 +297,7 @@ void mtu3_start(struct mtu3 *mtu)

		mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);

		/*
		* When disable U2 port, USB2_CSR's register will be reset to
		* default value after re-enable it again(HS is enabled by default).
		* So if force mac to work as FS, disable HS function.
		*/
		if (mtu->max_speed == USB_SPEED_FULL)
		mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
		mtu3_csr_init(mtu);

		/* Initialize the default interrupts */
		mtu3_intr_enable(mtu);
		@@ -572,39 +596,18 @@ static void mtu3_set_speed(struct mtu3 *mtu)

		static void mtu3_regs_init(struct mtu3 *mtu)
		{

		void __iomem *mbase = mtu->mac_base;

		/* be sure interrupts are disabled before registration of ISR */
		mtu3_intr_disable(mtu);
		mtu3_intr_status_clear(mtu);

		if (mtu->is_u3_ip) {
		/* disable LGO_U1/U2 by default */
		mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
		SW_U1_REQUEST_ENABLE \| SW_U2_REQUEST_ENABLE);
		/* enable accept LGO_U1/U2 link command from host */
		mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
		SW_U1_ACCEPT_ENABLE \| SW_U2_ACCEPT_ENABLE);
		/* device responses to u3_exit from host automatically */
		mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
		/* automatically build U2 link when U3 detect fail */
		mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
		/* auto clear SOFT_CONN when clear USB3_EN if work as HS */
		mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
		}

		mtu3_set_speed(mtu);
		mtu3_csr_init(mtu);

		/* delay about 0.1us from detecting reset to send chirp-K */
		mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
		/* U2/U3 detected by HW */
		mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
		/* vbus detected by HW */
		mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN \| VBUS_ON);
		/* enable automatical HWRW from L1 */
		mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE);

		/* use new QMU format when HW version >= 0x1003 */
		if (mtu->gen2cp)
		mtu3_writel(mbase, U3D_QFCR, ~0x0);

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