Merge tag 'omap-for-v3.11/gpmc-signed' of... (f54ffe0f) · Commits · 戴 / test

Documentation/devicetree/bindings/bus/ti-gpmc.txt

+0 −1

Original line number	Diff line number	Diff line
		@@ -95,7 +95,6 @@ GPMC chip-select settings properties for child nodes. All are optional.
		- gpmc,burst-wrap Enables wrap bursting
		- gpmc,burst-read Enables read page/burst mode
		- gpmc,burst-write Enables write page/burst mode
		- gpmc,device-nand Device is NAND
		- gpmc,device-width Total width of device(s) connected to a GPMC
		chip-select in bytes. The GPMC supports 8-bit
		and 16-bit devices and so this property must be

Documentation/devicetree/bindings/mtd/gpmc-nand.txt

+8 −0

Original line number	Diff line number	Diff line
		@@ -29,6 +29,13 @@ Optional properties:
		"bch4" 4-bit BCH ecc code
		"bch8" 8-bit BCH ecc code

		- ti,nand-xfer-type: A string setting the data transfer type. One of:

		"prefetch-polled" Prefetch polled mode (default)
		"polled" Polled mode, without prefetch
		"prefetch-dma" Prefetch enabled sDMA mode
		"prefetch-irq" Prefetch enabled irq mode

		- elm_id: Specifies elm device node. This is required to support BCH
		error correction using ELM module.

		@@ -55,6 +62,7 @@ Example for an AM33xx board:
		reg = <0 0 0>; /* CS0, offset 0 */
		nand-bus-width = <16>;
		ti,nand-ecc-opt = "bch8";
		ti,nand-xfer-type = "polled";

		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;

arch/arm/boot/dts/omap3430-sdp.dts

+0 −1

Original line number	Diff line number	Diff line
		@@ -105,7 +105,6 @@
		nand-bus-width = <8>;

		ti,nand-ecc-opt = "sw";
		gpmc,device-nand;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <36>;
		gpmc,cs-wr-off-ns = <36>;

arch/arm/mach-omap2/board-flash.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -112,6 +112,9 @@ struct gpmc_timings nand_default_timings[1] = {
		.cs_rd_off = 36,
		.cs_wr_off = 36,

		.we_on = 6,
		.oe_on = 6,

		.adv_on = 6,
		.adv_rd_off = 24,
		.adv_wr_off = 36,

arch/arm/mach-omap2/gpmc-nand.c

+3 −41

Original line number	Diff line number	Diff line
		@@ -43,44 +43,6 @@ static struct platform_device gpmc_nand_device = {
		.resource = gpmc_nand_resource,
		};

		static int omap2_nand_gpmc_retime(
		struct omap_nand_platform_data *gpmc_nand_data,
		struct gpmc_timings *gpmc_t)
		{
		struct gpmc_timings t;
		int err;

		memset(&t, 0, sizeof(t));
		t.sync_clk = gpmc_t->sync_clk;
		t.cs_on = gpmc_t->cs_on;
		t.adv_on = gpmc_t->adv_on;

		/* Read */
		t.adv_rd_off = gpmc_t->adv_rd_off;
		t.oe_on = t.adv_on;
		t.access = gpmc_t->access;
		t.oe_off = gpmc_t->oe_off;
		t.cs_rd_off = gpmc_t->cs_rd_off;
		t.rd_cycle = gpmc_t->rd_cycle;

		/* Write */
		t.adv_wr_off = gpmc_t->adv_wr_off;
		t.we_on = t.oe_on;
		if (cpu_is_omap34xx()) {
		t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus;
		t.wr_access = gpmc_t->wr_access;
		}
		t.we_off = gpmc_t->we_off;
		t.cs_wr_off = gpmc_t->cs_wr_off;
		t.wr_cycle = gpmc_t->wr_cycle;

		err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
		if (err)
		return err;

		return 0;
		}

		static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
		{
		/* support only OMAP3 class */
		@@ -131,7 +93,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
		gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);

		if (gpmc_t) {
		err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t);
		err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
		if (err < 0) {
		dev_err(dev, "Unable to set gpmc timings: %d\n", err);
		return err;
		@@ -140,8 +102,6 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
		if (gpmc_nand_data->of_node) {
		gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
		} else {
		s.device_nand = true;

		/* Enable RD PIN Monitoring Reg */
		if (gpmc_nand_data->dev_ready) {
		s.wait_on_read = true;
		@@ -149,6 +109,8 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
		}
		}

		s.device_nand = true;

		if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
		s.device_width = GPMC_DEVWIDTH_16BIT;
		else

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