Commit f536579c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-fixes-5.3-2019-08-07' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 



drm-fixes-5.3-2019-08-07:

amdgpu:
- Fixes VCN to handle the latest navi10 firmware
- Fixes for fan control on navi10
- Properly handle SMU metrics table on navi10
- Fix a resume regression on Stoney

amdkfd:
- Revert new GWS ioctl.  It's not ready.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190807184221.3323-1-alexander.deucher@amd.com
parents abffedaa 4b3e30ed

drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h

+0 −1
Original line number Diff line number Diff line
@@ -32,7 +32,6 @@ struct amdgpu_gds { 
	uint32_t gws_size;

	uint32_t oa_size;

	uint32_t gds_compute_max_wave_id;

	uint32_t vgt_gs_max_wave_id;

};



struct amdgpu_gds_reg_offset {

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#define AMDGPU_VCN_FIRMWARE_OFFSET	256

#define AMDGPU_VCN_MAX_ENC_RINGS	3



#define VCN_DEC_KMD_CMD 		0x80000000

#define VCN_DEC_CMD_FENCE		0x00000000

#define VCN_DEC_CMD_TRAP		0x00000001

#define VCN_DEC_CMD_WRITE_REG		0x00000004

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+1 −11
Original line number Diff line number Diff line
@@ -4206,15 +4206,6 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 
	unsigned vmid = AMDGPU_JOB_GET_VMID(job);

	u32 header, control = 0;



	/* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS.

	 * This resets the wave ID counters. (needed by transform feedback)

	 * TODO: This might only be needed on a VMID switch when we change

	 *       the GDS OA mapping, not sure.

	 */

	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

	amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID);

	amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id);



	if (ib->flags & AMDGPU_IB_FLAG_CE)

		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);

	else
@@ -4961,7 +4952,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 
		5 + /* HDP_INVL */

		8 + 8 + /* FENCE x2 */

		2, /* SWITCH_BUFFER */

	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_gfx */

	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */

	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,

	.emit_fence = gfx_v10_0_ring_emit_fence,

	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
@@ -5112,7 +5103,6 @@ static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 
	default:

		adev->gds.gds_size = 0x10000;

		adev->gds.gds_compute_max_wave_id = 0x4ff;

		adev->gds.vgt_gs_max_wave_id = 0x3ff;

		break;

	}

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+40 −0
Original line number Diff line number Diff line
@@ -1321,6 +1321,39 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) 
	return 0;

}



static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev)

{

	int r;



	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);

	if (unlikely(r != 0))

		return r;



	r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,

			AMDGPU_GEM_DOMAIN_VRAM);

	if (!r)

		adev->gfx.rlc.clear_state_gpu_addr =

			amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);



	amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);



	return r;

}



static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev)

{

	int r;



	if (!adev->gfx.rlc.clear_state_obj)

		return;



	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);

	if (likely(r == 0)) {

		amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);

		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);

	}

}



static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)

{

	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
@@ -4785,6 +4818,10 @@ static int gfx_v8_0_hw_init(void *handle) 
	gfx_v8_0_init_golden_registers(adev);

	gfx_v8_0_constants_init(adev);



	r = gfx_v8_0_csb_vram_pin(adev);

	if (r)

		return r;



	r = adev->gfx.rlc.funcs->resume(adev);

	if (r)

		return r;
@@ -4901,6 +4938,9 @@ static int gfx_v8_0_hw_fini(void *handle) 
	else

		pr_err("rlc is busy, skip halt rlc\n");

	amdgpu_gfx_rlc_exit_safe_mode(adev);



	gfx_v8_0_csb_vram_unpin(adev);



	return 0;

}

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

+37 −7
Original line number Diff line number Diff line
@@ -1485,7 +1485,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));

	amdgpu_ring_write(ring, 0);

	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));

	amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));

}



/**
@@ -1498,7 +1498,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 
static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)

{

	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));

	amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));

}



/**
@@ -1543,7 +1543,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 
	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);



	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));

	amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));



	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));

	amdgpu_ring_write(ring, 0);
@@ -1553,7 +1553,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 


	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));



	amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));

}



/**
@@ -1597,7 +1597,7 @@ static void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 


	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));



	amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));

}



static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
@@ -1626,7 +1626,7 @@ static void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 


	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));



	amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));

}



/**
@@ -2079,6 +2079,36 @@ static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev, 
	return 0;

}



static int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;

	uint32_t tmp = 0;

	unsigned i;

	int r;



	WREG32(adev->vcn.external.scratch9, 0xCAFEDEAD);

	r = amdgpu_ring_alloc(ring, 4);

	if (r)

		return r;

	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));

	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));

	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));

	amdgpu_ring_write(ring, 0xDEADBEEF);

	amdgpu_ring_commit(ring);

	for (i = 0; i < adev->usec_timeout; i++) {

		tmp = RREG32(adev->vcn.external.scratch9);

		if (tmp == 0xDEADBEEF)

			break;

		DRM_UDELAY(1);

	}



	if (i >= adev->usec_timeout)

		r = -ETIMEDOUT;



	return r;

}





static int vcn_v2_0_set_powergating_state(void *handle,

					  enum amd_powergating_state state)

{
@@ -2142,7 +2172,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { 
	.emit_ib = vcn_v2_0_dec_ring_emit_ib,

	.emit_fence = vcn_v2_0_dec_ring_emit_fence,

	.emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,

	.test_ring = amdgpu_vcn_dec_ring_test_ring,

	.test_ring = vcn_v2_0_dec_ring_test_ring,

	.test_ib = amdgpu_vcn_dec_ring_test_ib,

	.insert_nop = vcn_v2_0_dec_ring_insert_nop,

	.insert_start = vcn_v2_0_dec_ring_insert_start,

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