coresight: tmc-etr: Handle memory errors (f52ff9b7) · Commits · 戴 / test

We have so far ignored the memory errors, assuming that we have perfect hardware and driver. Let us handle the memory errors reported by the TMC ETR in status and truncate the buffer. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:

Suzuki K Poulose <suzuki.poulose@arm.com> [Removed ASCII smiley face from changelog] Signed-off-by:

Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-6-mathieu.poirier@linaro.org Signed-off-by:

Greg Kroah-Hartman <gregkh@linuxfoundation.org>

drivers/hwtracing/coresight/coresight-tmc-etr.c

+13 −0

Original line number	Diff line number	Diff line
		@@ -928,6 +928,19 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
		rrp = tmc_read_rrp(drvdata);
		rwp = tmc_read_rwp(drvdata);
		status = readl_relaxed(drvdata->base + TMC_STS);

		/*
		* If there were memory errors in the session, truncate the
		* buffer.
		*/
		if (WARN_ON_ONCE(status & TMC_STS_MEMERR)) {
		dev_dbg(&drvdata->csdev->dev,
		"tmc memory error detected, truncating buffer\n");
		etr_buf->len = 0;
		etr_buf->full = 0;
		return;
		}

		etr_buf->full = status & TMC_STS_FULL;

		WARN_ON(!etr_buf->ops \|\| !etr_buf->ops->sync);

drivers/hwtracing/coresight/coresight-tmc.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -47,6 +47,7 @@
		#define TMC_STS_TMCREADY_BIT 2
		#define TMC_STS_FULL BIT(0)
		#define TMC_STS_TRIGGERED BIT(1)
		#define TMC_STS_MEMERR BIT(5)
		/*
		* TMC_AXICTL - 0x110
		*

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