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Commit f4fcfa42 authored Apr 30, 2020 by Evan Quan Committed by Alex Deucher May 08, 2020

drm/amd/powerplay: perform PG ungate prior to CG ungate



Since gfxoff should be disabled first before trying to access those
GC registers.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 1fe48ec0

drivers/gpu/drm/amd/powerplay/amd_powerplay.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -319,12 +319,12 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
		if (*level & profile_mode_mask) {
		hwmgr->saved_dpm_level = hwmgr->dpm_level;
		hwmgr->en_umd_pstate = true;
		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
		AMD_IP_BLOCK_TYPE_GFX,
		AMD_CG_STATE_UNGATE);
		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
		AMD_IP_BLOCK_TYPE_GFX,
		AMD_PG_STATE_UNGATE);
		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
		AMD_IP_BLOCK_TYPE_GFX,
		AMD_CG_STATE_UNGATE);
		}
		} else {
		/* exit umd pstate, restore level, enable gfx cg*/

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -1744,12 +1744,12 @@ static int smu_enable_umd_pstate(void *handle,
		if (*level & profile_mode_mask) {
		smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
		smu_dpm_ctx->enable_umd_pstate = true;
		amdgpu_device_ip_set_clockgating_state(smu->adev,
		AMD_IP_BLOCK_TYPE_GFX,
		AMD_CG_STATE_UNGATE);
		amdgpu_device_ip_set_powergating_state(smu->adev,
		AMD_IP_BLOCK_TYPE_GFX,
		AMD_PG_STATE_UNGATE);
		amdgpu_device_ip_set_clockgating_state(smu->adev,
		AMD_IP_BLOCK_TYPE_GFX,
		AMD_CG_STATE_UNGATE);
		}
		} else {
		/* exit umd pstate, restore level, enable gfx cg*/

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