Commit f4e5b30d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 updates and fixes from Thomas Gleixner:

 - Fix the (late) fallout from the vector management rework causing
   hlist corruption and irq descriptor reference leaks caused by a
   missing sanity check.

   The straight forward fix triggered another long standing issue to
   surface. The pre rework code hid the issue due to being way slower,
   but now the chance that user space sees an EBUSY error return when
   updating irq affinities is way higher, though quite a bunch of
   userspace tools do not handle it properly despite the fact that EBUSY
   could be returned for at least 10 years.

   It turned out that the EBUSY return can be avoided completely by
   utilizing the existing delayed affinity update mechanism for irq
   remapped scenarios as well. That's a bit more error handling in the
   kernel, but avoids fruitless fingerpointing discussions with tool
   developers.

 - Decouple PHYSICAL_MASK from AMD SME as its going to be required for
   the upcoming Intel memory encryption support as well.

 - Handle legacy device ACPI detection properly for newer platforms

 - Fix the wrong argument ordering in the vector allocation tracepoint

 - Simplify the IDT setup code for the APIC=n case

 - Use the proper string helpers in the MTRR code

 - Remove a stale unused VDSO source file

 - Convert the microcode update lock to a raw spinlock as its used in
   atomic context.

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/intel_rdt: Enable CMT and MBM on new Skylake stepping
  x86/apic/vector: Print APIC control bits in debugfs
  genirq/affinity: Defer affinity setting if irq chip is busy
  x86/platform/uv: Use apic_ack_irq()
  x86/ioapic: Use apic_ack_irq()
  irq_remapping: Use apic_ack_irq()
  x86/apic: Provide apic_ack_irq()
  genirq/migration: Avoid out of line call if pending is not set
  genirq/generic_pending: Do not lose pending affinity update
  x86/apic/vector: Prevent hlist corruption and leaks
  x86/vector: Fix the args of vector_alloc tracepoint
  x86/idt: Simplify the idt_setup_apic_and_irq_gates()
  x86/platform/uv: Remove extra parentheses
  x86/mm: Decouple dynamic __PHYSICAL_MASK from AMD SME
  x86: Mark native_set_p4d() as __always_inline
  x86/microcode: Make the late update update_lock a raw lock for RT
  x86/mtrr: Convert to use strncpy_from_user() helper
  x86/mtrr: Convert to use match_string() helper
  x86/vdso: Remove unused file
  x86/i8237: Register device based on FADT legacy boot flag
parents a2211de0 1d9f3e20

arch/x86/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -334,6 +334,9 @@ config ARCH_SUPPORTS_UPROBES 
config FIX_EARLYCON_MEM

	def_bool y



config DYNAMIC_PHYSICAL_MASK

	bool



config PGTABLE_LEVELS

	int

	default 5 if X86_5LEVEL
@@ -1486,6 +1489,7 @@ config ARCH_HAS_MEM_ENCRYPT 
config AMD_MEM_ENCRYPT

	bool "AMD Secure Memory Encryption (SME) support"

	depends on X86_64 && CPU_SUP_AMD

	select DYNAMIC_PHYSICAL_MASK

	---help---

	  Say yes to enable support for the encryption of system memory.

	  This requires an AMD processor that supports Secure Memory

arch/x86/boot/compressed/kaslr_64.c

+5 −0
Original line number Diff line number Diff line
@@ -69,6 +69,8 @@ static struct alloc_pgt_data pgt_data; 
/* The top level page table entry pointer. */

static unsigned long top_level_pgt;



phys_addr_t physical_mask = (1ULL << __PHYSICAL_MASK_SHIFT) - 1;



/*

 * Mapping information structure passed to kernel_ident_mapping_init().

 * Due to relocation, pointers must be assigned at run time not build time.
@@ -81,6 +83,9 @@ void initialize_identity_maps(void) 
	/* If running as an SEV guest, the encryption mask is required. */

	set_sev_encryption_mask();



	/* Exclude the encryption mask from __PHYSICAL_MASK */

	physical_mask &= ~sme_me_mask;



	/* Init mapping_info with run-time function/buffer pointers. */

	mapping_info.alloc_pgt_page = alloc_pgt_page;

	mapping_info.context = &pgt_data;

arch/x86/include/asm/apic.h

+2 −0
Original line number Diff line number Diff line
@@ -436,6 +436,8 @@ static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} 


#endif /* CONFIG_X86_LOCAL_APIC */



extern void apic_ack_irq(struct irq_data *data);



static inline void ack_APIC_irq(void)

{

	/*

arch/x86/include/asm/page_types.h

+7 −1
Original line number Diff line number Diff line
@@ -17,7 +17,6 @@ 
#define PUD_PAGE_SIZE		(_AC(1, UL) << PUD_SHIFT)

#define PUD_PAGE_MASK		(~(PUD_PAGE_SIZE-1))



#define __PHYSICAL_MASK		((phys_addr_t)(__sme_clr((1ULL << __PHYSICAL_MASK_SHIFT) - 1)))

#define __VIRTUAL_MASK		((1UL << __VIRTUAL_MASK_SHIFT) - 1)



/* Cast *PAGE_MASK to a signed type so that it is sign-extended if
@@ -55,6 +54,13 @@ 


#ifndef __ASSEMBLY__



#ifdef CONFIG_DYNAMIC_PHYSICAL_MASK

extern phys_addr_t physical_mask;

#define __PHYSICAL_MASK		physical_mask

#else

#define __PHYSICAL_MASK		((phys_addr_t)((1ULL << __PHYSICAL_MASK_SHIFT) - 1))

#endif



extern int devmem_is_allowed(unsigned long pagenr);



extern unsigned long max_low_pfn_mapped;

arch/x86/include/asm/pgtable_64.h

+2 −2
Original line number Diff line number Diff line
@@ -216,7 +216,7 @@ static inline pgd_t pti_set_user_pgd(pgd_t *pgdp, pgd_t pgd) 
}

#endif



static inline void native_set_p4d(p4d_t *p4dp, p4d_t p4d)

static __always_inline void native_set_p4d(p4d_t *p4dp, p4d_t p4d)

{

	pgd_t pgd;
@@ -230,7 +230,7 @@ static inline void native_set_p4d(p4d_t *p4dp, p4d_t p4d) 
	*p4dp = native_make_p4d(native_pgd_val(pgd));

}



static inline void native_p4d_clear(p4d_t *p4d)

static __always_inline void native_p4d_clear(p4d_t *p4d)

{

	native_set_p4d(p4d, native_make_p4d(0));

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE