Commit f4ca7a92 authored May 24, 2019 by Biao Huang Committed by David S. Miller May 25, 2019

net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail



1. the frequency of csr clock is 66.5MHz, so the csr_clk value should
be 0 other than 5.
2. the csr_clk can be got from device tree, so remove initialization here.

Fixes: 9992f37e ("stmmac: dwmac-mediatek: add support for mt2712")
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent 5e7f7fc5

drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c

+0 −2

Original line number	Diff line number	Diff line
		@@ -346,8 +346,6 @@ static int mediatek_dwmac_probe(struct platform_device *pdev)
		return PTR_ERR(plat_dat);

		plat_dat->interface = priv_plat->phy_mode;
		/* clk_csr_i = 250-300MHz & MDC = clk_csr_i/124 */
		plat_dat->clk_csr = 5;
		plat_dat->has_gmac4 = 1;
		plat_dat->has_gmac = 0;
		plat_dat->pmt = 0;

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