Commit f4c87b7a authored by Alban Bedel's avatar Alban Bedel Committed by Ralf Baechle
Browse files

MIPS: ath79: Fix the ar913x reference clock rate 



The reference clock on ar913x is at 40MHz and not 5MHz. The current
implementation use the wrong reference rate because it doesn't take
the PLL divider in account. But if we fix the code to use the divider
it becomes identical with the implementation for ar724x, so just drop
the broken ar913x implementation.

Signed-off-by: default avatarAlban Bedel <albeu@free.fr>
Tested-by: default avatarAntony Pavlov <antonynpavlov@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12871/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c338d59d

arch/mips/ath79/clock.c

+1 −37
Original line number Diff line number Diff line
@@ -27,7 +27,6 @@ 


#define AR71XX_BASE_FREQ	40000000

#define AR724X_BASE_FREQ	40000000

#define AR913X_BASE_FREQ	5000000



static struct clk *clks[3];

static struct clk_onecell_data clk_data = {
@@ -123,39 +122,6 @@ static void __init ar724x_clocks_init(void) 
	clk_add_alias("uart", NULL, "ahb", NULL);

}



static void __init ar913x_clocks_init(void)

{

	unsigned long ref_rate;

	unsigned long cpu_rate;

	unsigned long ddr_rate;

	unsigned long ahb_rate;

	u32 pll;

	u32 freq;

	u32 div;



	ref_rate = AR913X_BASE_FREQ;

	pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);



	div = ((pll >> AR913X_PLL_FB_SHIFT) & AR913X_PLL_FB_MASK);

	freq = div * ref_rate;



	cpu_rate = freq;



	div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;

	ddr_rate = freq / div;



	div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;

	ahb_rate = cpu_rate / div;



	ath79_add_sys_clkdev("ref", ref_rate);

	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);

	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);

	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);



	clk_add_alias("wdt", NULL, "ahb", NULL);

	clk_add_alias("uart", NULL, "ahb", NULL);

}



static void __init ar933x_clocks_init(void)

{

	unsigned long ref_rate;
@@ -443,10 +409,8 @@ void __init ath79_clocks_init(void) 
{

	if (soc_is_ar71xx())

		ar71xx_clocks_init();

	else if (soc_is_ar724x())

	else if (soc_is_ar724x() || soc_is_ar913x())

		ar724x_clocks_init();

	else if (soc_is_ar913x())

		ar913x_clocks_init();

	else if (soc_is_ar933x())

		ar933x_clocks_init();

	else if (soc_is_ar934x())

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