Unverified Commit f4c4b1bb authored by Shengjiu Wang's avatar Shengjiu Wang Committed by Mark Brown
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ASoC: fsl_sai: Set SAI Channel Mode to Output Mode 



Transmit data pins will output zero when slots are masked or channels
are disabled. In CHMOD TDM mode, transmit data pins are tri-stated when
slots are masked or channels are disabled. When data pins are tri-stated,
there is noise on some channels when FS clock value is high and data is
read while fsclk is transitioning from high to low.

Signed-off-by: default avatarCosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Signed-off-by: default avatarShengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: default avatarNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/1599112427-22038-1-git-send-email-shengjiu.wang@nxp.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 770f58d7

sound/soc/fsl/fsl_sai.c

+8 −2
Original line number Diff line number Diff line
@@ -489,6 +489,10 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 


	val_cr4 |= FSL_SAI_CR4_FRSZ(slots);



	/* Set to output mode to avoid tri-stated data pins */

	if (tx)

		val_cr4 |= FSL_SAI_CR4_CHMOD;



	/*

	 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will

	 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
@@ -497,7 +501,8 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 


	if (!sai->is_slave_mode && fsl_sai_dir_is_synced(sai, adir)) {

		regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),

				   FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,

				   FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |

				   FSL_SAI_CR4_CHMOD_MASK,

				   val_cr4);

		regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),

				   FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
@@ -508,7 +513,8 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 
			   FSL_SAI_CR3_TRCE_MASK,

			   FSL_SAI_CR3_TRCE((1 << pins) - 1));

	regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),

			   FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,

			   FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |

			   FSL_SAI_CR4_CHMOD_MASK,

			   val_cr4);

	regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),

			   FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |

sound/soc/fsl/fsl_sai.h

+2 −0
Original line number Diff line number Diff line
@@ -119,6 +119,8 @@ 
#define FSL_SAI_CR4_FRSZ_MASK	(0x1f << 16)

#define FSL_SAI_CR4_SYWD(x)	(((x) - 1) << 8)

#define FSL_SAI_CR4_SYWD_MASK	(0x1f << 8)

#define FSL_SAI_CR4_CHMOD       BIT(5)

#define FSL_SAI_CR4_CHMOD_MASK  BIT(5)

#define FSL_SAI_CR4_MF		BIT(4)

#define FSL_SAI_CR4_FSE		BIT(3)

#define FSL_SAI_CR4_FSP		BIT(1)

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