Commit f4be3c67 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'tegra-for-4.3-dt' of... 

Merge tag 'tegra-for-4.3-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt

ARM: tegra: Devicetree changes for v4.3-rc1

Enables CPU frequency scaling on Jetson TK1 and enables the GK20A GPU on
Venice2 and Jetson TK1. This also enables support for the PMU hardware
found on Tegra124, which among other things, can be used for performance
measurements.

* tag 'tegra-for-4.3-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux

:
  ARM: tegra: Add gpio-ranges property
  ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114
  ARM: tegra: Add Tegra124 PMU support
  ARM: tegra: jetson-tk1: Add GK20A GPU DT node
  ARM: tegra: venice2: Add GK20A GPU DT node
  ARM: tegra: Add IOMMU node to GK20A
  ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
  ARM: tegra: Add entries for cpufreq on Tegra124
  ARM: tegra: Enable the DFLL on the Jetson TK1
  ARM: tegra: Add the DFLL to Tegra124 device tree
  pinctrl: tegra: Only set the gpio range if needed
  clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
  clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend
  clk: tegra: Add Tegra124 DFLL clocksource platform driver
  clk: tegra: Add DFLL DVCO reset control for Tegra124
  clk: tegra: Introduce ability for SoC-specific reset control callbacks
  clk: tegra: Add functions for parsing CVB tables
  clk: tegra: Add closed loop support for the DFLL
  clk: tegra: Add library for the DFLL clock source (open-loop mode)
  clk: tegra: Add binding for the Tegra124 DFLL clocksource

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 99650c25 17cdddf0

Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt

0 → 100644
+79 −0
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NVIDIA Tegra124 DFLL FCPU clocksource



This binding uses the common clock binding:

Documentation/devicetree/bindings/clock/clock-bindings.txt



The DFLL IP block on Tegra is a root clocksource designed for clocking

the fast CPU cluster. It consists of a free-running voltage controlled

oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop

control module that will automatically adjust the VDD_CPU voltage by

communicating with an off-chip PMIC either via an I2C bus or via PWM signals.

Currently only the I2C mode is supported by these bindings.



Required properties:

- compatible : should be "nvidia,tegra124-dfll"

- reg : Defines the following set of registers, in the order listed:

        - registers for the DFLL control logic.

        - registers for the I2C output logic.

        - registers for the integrated I2C master controller.

        - look-up table RAM for voltage register values.

- interrupts: Should contain the DFLL block interrupt.

- clocks: Must contain an entry for each entry in clock-names.

  See clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - soc: Clock source for the DFLL control logic.

  - ref: The closed loop reference clock

  - i2c: Clock source for the integrated I2C master.

- resets: Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names: Must include the following entries:

  - dvco: Reset control for the DFLL DVCO.

- #clock-cells: Must be 0.

- clock-output-names: Name of the clock output.

- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL

  hardware will start controlling. The regulator will be queried for

  the I2C register, control values and supported voltages.



Required properties for the control loop parameters:

- nvidia,sample-rate: Sample rate of the DFLL control loop.

- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.

- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.

- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.

- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.

- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.



Optional properties for the control loop parameters:

- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.



Required properties for I2C mode:

- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.



Example:



clock@0,70110000 {

        compatible = "nvidia,tegra124-dfll";

        reg = <0 0x70110000 0 0x100>, /* DFLL control */

              <0 0x70110000 0 0x100>, /* I2C output control */

              <0 0x70110100 0 0x100>, /* Integrated I2C controller */

              <0 0x70110200 0 0x100>; /* Look-up table RAM */

        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,

                 <&tegra_car TEGRA124_CLK_DFLL_REF>,

                 <&tegra_car TEGRA124_CLK_I2C5>;

        clock-names = "soc", "ref", "i2c";

        resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;

        reset-names = "dvco";

        #clock-cells = <0>;

        clock-output-names = "dfllCPU_out";

        vdd-cpu-supply = <&vdd_cpu>;

        status = "okay";



        nvidia,sample-rate = <12500>;

        nvidia,droop-ctrl = <0x00000f00>;

        nvidia,force-mode = <1>;

        nvidia,cf = <10>;

        nvidia,ci = <0>;

        nvidia,cg = <2>;



        nvidia,i2c-fs-rate = <400000>;

};

arch/arm/boot/dts/tegra114.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -214,9 +214,9 @@ 
		#dma-cells = <1>;

	};



	ahb: ahb@6000c004 {

	ahb: ahb@6000c000 {

		compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";

		reg = <0x6000c004 0x14c>;

		reg = <0x6000c000 0x150>;

	};



	gpio: gpio@6000d000 {
@@ -234,6 +234,7 @@ 
		gpio-controller;

		#interrupt-cells = <2>;

		interrupt-controller;

		gpio-ranges = <&pinmux 0 0 246>;

	};



	apbmisc@70000800 {

arch/arm/boot/dts/tegra124-jetson-tk1.dts

+23 −2
Original line number Diff line number Diff line
@@ -53,6 +53,14 @@ 
		};

	};



	gpu@0,57000000 {

		/*

		 * Node left disabled on purpose - the bootloader will enable

		 * it after having set the VPR up

		 */

		vdd-supply = <&vdd_gpu>;

	};



	pinmux: pinmux@0,70000868 {

		pinctrl-names = "boot";

		pinctrl-0 = <&state_boot>;
@@ -1462,7 +1470,7 @@ 
				vin-ldo9-10-supply = <&vdd_5v0_sys>;

				vin-ldo11-supply = <&vdd_3v3_run>;



				sd0 {

				vdd_cpu: sd0 {

					regulator-name = "+VDD_CPU_AP";

					regulator-min-microvolt = <700000>;

					regulator-max-microvolt = <1400000>;
@@ -1514,7 +1522,7 @@ 
					regulator-always-on;

				};



				sd6 {

				vdd_gpu: sd6 {

					regulator-name = "+VDD_GPU_AP";

					regulator-min-microvolt = <650000>;

					regulator-max-microvolt = <1200000>;
@@ -1694,6 +1702,13 @@ 
		non-removable;

	};



	/* CPU DFLL clock */

	clock@0,70110000 {

		status = "okay";

		vdd-cpu-supply = <&vdd_cpu>;

		nvidia,i2c-fs-rate = <400000>;

	};



	ahub@0,70300000 {

		i2s@0,70301100 {

			status = "okay";
@@ -1732,6 +1747,12 @@ 
		};

	};



	cpus {

		cpu@0 {

			vdd-cpu-supply = <&vdd_cpu>;

		};

	};



	gpio-keys {

		compatible = "gpio-keys";

arch/arm/boot/dts/tegra124-venice2.dts

+9 −1
Original line number Diff line number Diff line
@@ -43,6 +43,14 @@ 
		};

	};



	gpu@0,57000000 {

		/*

		 * Node left disabled on purpose - the bootloader will enable

		 * it after having set the VPR up

		 */

		vdd-supply = <&vdd_gpu>;

	};



	pinmux: pinmux@0,70000868 {

		pinctrl-names = "boot";

		pinctrl-0 = <&pinmux_boot>;
@@ -735,7 +743,7 @@ 
					regulator-always-on;

				};



				sd6 {

				vdd_gpu: sd6 {

					regulator-name = "+VDD_GPU_AP";

					regulator-min-microvolt = <650000>;

					regulator-max-microvolt = <1200000>;

arch/arm/boot/dts/tegra124.dtsi

+50 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
#include <dt-bindings/pinctrl/pinctrl-tegra.h>

#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/reset/tegra124-car.h>

#include <dt-bindings/thermal/tegra124-soctherm.h>



#include "skeleton.dtsi"
@@ -188,6 +189,9 @@ 
		clock-names = "gpu", "pwr";

		resets = <&tegra_car 184>;

		reset-names = "gpu";



		iommus = <&mc TEGRA_SWGROUP_GPU>;



		status = "disabled";

	};
@@ -254,6 +258,7 @@ 
		gpio-controller;

		#interrupt-cells = <2>;

		interrupt-controller;

		gpio-ranges = <&pinmux 0 0 251>;

	};



	apbdma: dma@0,60020000 {
@@ -702,6 +707,30 @@ 
		#thermal-sensor-cells = <1>;

	};



	dfll: clock@0,70110000 {

		compatible = "nvidia,tegra124-dfll";

		reg = <0 0x70110000 0 0x100>, /* DFLL control */

		      <0 0x70110000 0 0x100>, /* I2C output control */

		      <0 0x70110100 0 0x100>, /* Integrated I2C controller */

		      <0 0x70110200 0 0x100>; /* Look-up table RAM */

		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,

			 <&tegra_car TEGRA124_CLK_DFLL_REF>,

			 <&tegra_car TEGRA124_CLK_I2C5>;

		clock-names = "soc", "ref", "i2c";

		resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;

		reset-names = "dvco";

		#clock-cells = <0>;

		clock-output-names = "dfllCPU_out";

		nvidia,sample-rate = <12500>;

		nvidia,droop-ctrl = <0x00000f00>;

		nvidia,force-mode = <1>;

		nvidia,cf = <10>;

		nvidia,ci = <0>;

		nvidia,cg = <2>;

		status = "disabled";

	};



	ahub@0,70300000 {

		compatible = "nvidia,tegra124-ahub";

		reg = <0x0 0x70300000 0x0 0x200>,
@@ -922,6 +951,15 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <0>;



			clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,

				 <&tegra_car TEGRA124_CLK_CCLK_LP>,

				 <&tegra_car TEGRA124_CLK_PLL_X>,

				 <&tegra_car TEGRA124_CLK_PLL_P>,

				 <&dfll>;

			clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";

			/* FIXME: what's the actual transition time? */

			clock-latency = <300000>;

		};



		cpu@1 {
@@ -943,6 +981,18 @@ 
		};

	};



	pmu {

		compatible = "arm,cortex-a15-pmu";

		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&{/cpus/cpu@0}>,

				     <&{/cpus/cpu@1}>,

				     <&{/cpus/cpu@2}>,

				     <&{/cpus/cpu@3}>;

	};



	thermal-zones {

		cpu {

			polling-delay-passive = <1000>;

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