Commit f4bbebf8 authored by Martin Leung's avatar Martin Leung Committed by Alex Deucher
Browse files

drm/amd/display: extending AUX SW Timeout 



[Why]
AUX takes longer to reply when using active DP-DVI dongle on some asics
resulting in up to 2000+ us edid read (timeout).

[How]
1. Adjust AUX poll to match spec
2. Extend the SW timeout. This does not affect normal
operation since we exit the loop as soon as AUX acks.

Signed-off-by: default avatarMartin Leung <martin.leung@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarJoshua Aberback <Joshua.Aberback@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 543c364d

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

+6 −3
Original line number Diff line number Diff line
@@ -190,6 +190,12 @@ static void submit_channel_request( 
				1,

				0);

	}



	REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);



	REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,

				10, aux110->timeout_period/10);



	/* set the delay and the number of bytes to write */



	/* The length include
@@ -242,9 +248,6 @@ static void submit_channel_request( 
		}

	}



	REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);

	REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,

				10, aux110->timeout_period/10);

	REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);

}

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

+3 −3
Original line number Diff line number Diff line
@@ -71,11 +71,11 @@ enum { /* This is the timeout as defined in DP 1.2a, 
	 * at most within ~240usec. That means,

	 * increasing this timeout will not affect normal operation,

	 * and we'll timeout after

	 * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 1600usec.

	 * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 2400usec.

	 * This timeout is especially important for

	 * resume from S3 and CTS.

	 * converters, resume from S3, and CTS.

	 */

	SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 4

	SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 6

};



struct dce_aux {

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