Commit f4aa3183 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Vinod Koul
Browse files

dmaengine: dw: extract dwc_chan_pause() for future use 



iDMA 32-bit has a special handling of the FIFO during pause() /
terminate_all(). Prepare code to implement that.

Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent be242f4e

drivers/dma/dw/core.c

+9 −5
Original line number Diff line number Diff line
@@ -927,22 +927,26 @@ static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) 
	return 0;

}



static int dwc_pause(struct dma_chan *chan)

static void dwc_chan_pause(struct dw_dma_chan *dwc)

{

	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);

	unsigned long		flags;

	unsigned int		count = 20;	/* timeout iterations */

	u32			cfglo;



	spin_lock_irqsave(&dwc->lock, flags);



	cfglo = channel_readl(dwc, CFG_LO);

	channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);

	while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)

		udelay(2);



	set_bit(DW_DMA_IS_PAUSED, &dwc->flags);

}



static int dwc_pause(struct dma_chan *chan)

{

	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);

	unsigned long		flags;



	spin_lock_irqsave(&dwc->lock, flags);

	dwc_chan_pause(dwc);

	spin_unlock_irqrestore(&dwc->lock, flags);



	return 0;

CRA Git | Maintained and supported by SUSTech CRA and CCSE