drm/i915/icl: WaModifyGamTlbPartitioning (f4a35714) · Commits · 戴 / test

Adjust default GAM TLB partitioning for performance reasons. v2: Only touch the bits that we really need v3: Rebased on top of the WA refactoring v4: - Added References (Mika) - Rebased v5: - Rebased - C, not lisp (Chris) - Correct reference number (Mika) References: HSDES#220160670 Signed-off-by:

Oscar Mateo <oscar.mateo@intel.com> Reviewed-by:

Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by:

Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-6-git-send-email-oscar.mateo@intel.com

drivers/gpu/drm/i915/i915_reg.h

+5 −0

Original line number	Diff line number	Diff line
		@@ -8263,6 +8263,11 @@ enum {
		#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
		#define DFR_DISABLE (1 << 9)

		#define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
		#define GEN11_HASH_CTRL_MASK (0x3 << 12 \| 0xf << 0)
		#define GEN11_HASH_CTRL_BIT0 (1 << 0)
		#define GEN11_HASH_CTRL_BIT4 (1 << 12)

		/* IVYBRIDGE DPF */
		#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
		#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)

drivers/gpu/drm/i915/intel_workarounds.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -715,6 +715,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
		I915_WRITE(GEN11_GLBLINVL,
		(I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) \|
		GEN11_BANK_HASH_ADDR_EXCL_BIT0);

		/* WaModifyGamTlbPartitioning:icl */
		I915_WRITE(GEN11_GACB_PERF_CTRL,
		(I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) \|
		GEN11_HASH_CTRL_BIT0 \| GEN11_HASH_CTRL_BIT4);
		}

		void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)

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