Commit f4986d25 authored by Ding Tianhong's avatar Ding Tianhong Committed by Jeff Kirsher
Browse files

Revert commit 1a8b6d76 ("net:add one common config...") 



The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING has been added
to indicate that Relaxed Ordering Attributes (RO) should not
be used for Transaction Layer Packets (TLP) targeted toward
these affected Root Port, it will clear the bit4 in the PCIe
Device Control register, so the PCIe device drivers could
query PCIe configuration space to determine if it can send
TLPs to Root Port with the Relaxed Ordering Attributes set.

With this new flag  we don't need the config ARCH_WANT_RELAX_ORDER
to control the Relaxed Ordering Attributes for the ixgbe drivers
just like the commit 1a8b6d76 ("net:add one common config...") did,
so revert this commit.

Signed-off-by: default avatarDing Tianhong <dingtianhong@huawei.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent a39221ce

arch/Kconfig

+0 −3
Original line number Original line Diff line number Diff line
@@ -937,9 +937,6 @@ config STRICT_MODULE_RWX 
	  and non-text memory will be made non-executable. This provides

	  and non-text memory will be made non-executable. This provides

	  protection against certain security exploits (e.g. writing to text)

	  protection against certain security exploits (e.g. writing to text)





config ARCH_WANT_RELAX_ORDER

	bool



config ARCH_HAS_REFCOUNT

config ARCH_HAS_REFCOUNT

	bool

	bool

	help

	help

arch/sparc/Kconfig

+0 −1
Original line number Original line Diff line number Diff line
@@ -44,7 +44,6 @@ config SPARC 
	select ARCH_HAS_SG_CHAIN

	select ARCH_HAS_SG_CHAIN

	select CPU_NO_EFFICIENT_FFS

	select CPU_NO_EFFICIENT_FFS

	select LOCKDEP_SMALL if LOCKDEP

	select LOCKDEP_SMALL if LOCKDEP

	select ARCH_WANT_RELAX_ORDER





config SPARC32

config SPARC32

	def_bool !64BIT

	def_bool !64BIT

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -366,7 +366,7 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 
	}

	}

	IXGBE_WRITE_FLUSH(hw);

	IXGBE_WRITE_FLUSH(hw);





#ifndef CONFIG_ARCH_WANT_RELAX_ORDER

#ifndef CONFIG_SPARC

	/* Disable relaxed ordering */

	/* Disable relaxed ordering */

	for (i = 0; i < hw->mac.max_tx_queues; i++) {

	for (i = 0; i < hw->mac.max_tx_queues; i++) {

		u32 regval;

		u32 regval;

CRA Git | Maintained and supported by SUSTech CRA and CCSE