drm/i915: Program SHPD_FILTER_CNT on CNP+ (f49108d0) · Commits · 戴 / test

The bspec tells us 'Program SHPD_FILTER_CNT with the "500 microseconds adjusted" value before enabling hotplug detection' on CNP+. We haven't been touching this register at all thus far, but we should probably follow the bspec's guidance. The register also exists on LPT and SPT, but there isn't any specific guidance I can find on how we should be programming it there so let's leave it be for now. Bspec: 4342 Bspec: 31297 Bspec: 8407 Bspec: 49305 Bspec: 50473 Signed-off-by:

Matt Roper <matthew.d.roper@intel.com> Reviewed-by:

José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191127221314.575575-3-matthew.d.roper@intel.com

drivers/gpu/drm/i915/i915_irq.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -2980,6 +2980,8 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
		hotplug_irqs = sde_ddi_mask \| sde_tc_mask;
		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, pins);

		I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);

		ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);

		icp_hpd_detection_setup(dev_priv, ddi_enable_mask, tc_enable_mask);
		@@ -3085,6 +3087,9 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
		{
		u32 hotplug_irqs, enabled_irqs;

		if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
		I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);

		hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);

drivers/gpu/drm/i915/i915_reg.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -8114,6 +8114,10 @@ enum {

		#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
		#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)

		#define SHPD_FILTER_CNT _MMIO(0xc4038)
		#define SHPD_FILTER_CNT_500_ADJ 0x001D9

		/* Icelake DSC Rate Control Range Parameter Registers */
		#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
		#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)

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