Commit f47fcad6 authored by Roger Quadros's avatar Roger Quadros
Browse files

memory: omap-gpmc: Introduce GPMC to NAND interface 



The OMAP GPMC module has certain registers dedicated for NAND
access and some NAND bits mixed with other GPMC functionality.

For the NAND dedicated registers we have the struct gpmc_nand_regs.

The NAND driver needs to access NAND specific bits from the
following non-dedicated registers
- EMPTYWRITEBUFFERSTATUS from GPMC_STATUS

For accessing these bits we introduce the struct gpmc_nand_ops.

Add gpmc_omap_get_nand_ops() that returns the gpmc_nand_ops along
with updating the gpmc_nand_regs. This API will be called by the
OMAP NAND driver to access the necessary bits in GPMC register space.

Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
Acked-by: default avatarTony Lindgren <tony@atomide.com>
parent fabe7d77

drivers/memory/omap-gpmc.c

+21 −0
Original line number Diff line number Diff line
@@ -1118,6 +1118,27 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) 
	}

}



static struct gpmc_nand_ops nand_ops;



/**

 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface

 * @regs: the GPMC NAND register map exclusive for NAND use.

 * @cs: GPMC chip select number on which the NAND sits. The

 *      register map returned will be specific to this chip select.

 *

 * Returns NULL on error e.g. invalid cs.

 */

struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)

{

	if (cs >= gpmc_cs_num)

		return NULL;



	gpmc_update_nand_reg(reg, cs);



	return &nand_ops;

}

EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);



int gpmc_get_client_irq(unsigned irq_config)

{

	int i;

include/linux/omap-gpmc.h

+33 −2
Original line number Diff line number Diff line
@@ -14,14 +14,45 @@ 
#define GPMC_IRQ_FIFOEVENTENABLE	0x01

#define GPMC_IRQ_COUNT_EVENT		0x02



/**

 * gpmc_nand_ops - Interface between NAND and GPMC

 * @nand_write_buffer_empty: get the NAND write buffer empty status.

 */

struct gpmc_nand_ops {

	bool (*nand_writebuffer_empty)(void);

};



struct gpmc_nand_regs;



#if IS_ENABLED(CONFIG_OMAP_GPMC)

struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *regs,

					     int cs);

#else

static inline gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *regs,

						    int cs)

{

	return NULL;

}

#endif /* CONFIG_OMAP_GPMC */



/*--------------------------------*/



/* deprecated APIs */

#if IS_ENABLED(CONFIG_OMAP_GPMC)

void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);

#else

static inline void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)

{

}

#endif /* CONFIG_OMAP_GPMC */

/*--------------------------------*/



extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,

			     struct gpmc_settings *gpmc_s,

			     struct gpmc_device_timings *dev_t);



struct gpmc_nand_regs;

struct device_node;



extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);

extern int gpmc_get_client_irq(unsigned irq_config);



extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);

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