Commit f44d23b9 authored by Ofir Bitton's avatar Ofir Bitton Committed by Oded Gabbay
Browse files

habanalabs: set clock gating according to mask 



Once clock gating is set we enable clock gating according to mask,
we should also disable clock gating according to relevant bits.

Signed-off-by: default avatarOfir Bitton <obitton@habana.ai>
Reviewed-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
parent 1cff1197

drivers/misc/habanalabs/gaudi/gaudi.c

+21 −23
Original line number Diff line number Diff line
@@ -2508,6 +2508,7 @@ static void gaudi_set_clock_gating(struct hl_device *hdev) 
{

	struct gaudi_device *gaudi = hdev->asic_specific;

	u32 qman_offset;

	bool enable;

	int i;



	/* In case we are during debug session, don't enable the clock gate
@@ -2517,46 +2518,43 @@ static void gaudi_set_clock_gating(struct hl_device *hdev) 
		return;



	for (i = GAUDI_PCI_DMA_1, qman_offset = 0 ; i < GAUDI_HBM_DMA_1 ; i++) {

		if (!(hdev->clock_gating_mask &

					(BIT_ULL(gaudi_dma_assignment[i]))))

			continue;

		enable = !!(hdev->clock_gating_mask &

				(BIT_ULL(gaudi_dma_assignment[i])));



		qman_offset = gaudi_dma_assignment[i] * DMA_QMAN_OFFSET;

		WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset, QMAN_CGM1_PWR_GATE_EN);

		WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset,

				enable ? QMAN_CGM1_PWR_GATE_EN : 0);

		WREG32(mmDMA0_QM_CGM_CFG + qman_offset,

				QMAN_UPPER_CP_CGM_PWR_GATE_EN);

				enable ? QMAN_UPPER_CP_CGM_PWR_GATE_EN : 0);

	}



	for (i = GAUDI_HBM_DMA_1 ; i < GAUDI_DMA_MAX ; i++) {

		if (!(hdev->clock_gating_mask &

					(BIT_ULL(gaudi_dma_assignment[i]))))

			continue;

		enable = !!(hdev->clock_gating_mask &

				(BIT_ULL(gaudi_dma_assignment[i])));



		qman_offset = gaudi_dma_assignment[i] * DMA_QMAN_OFFSET;

		WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset, QMAN_CGM1_PWR_GATE_EN);

		WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset,

				enable ? QMAN_CGM1_PWR_GATE_EN : 0);

		WREG32(mmDMA0_QM_CGM_CFG + qman_offset,

				QMAN_COMMON_CP_CGM_PWR_GATE_EN);

				enable ? QMAN_COMMON_CP_CGM_PWR_GATE_EN : 0);

	}



	if (hdev->clock_gating_mask & (BIT_ULL(GAUDI_ENGINE_ID_MME_0))) {

		WREG32(mmMME0_QM_CGM_CFG1, QMAN_CGM1_PWR_GATE_EN);

		WREG32(mmMME0_QM_CGM_CFG, QMAN_COMMON_CP_CGM_PWR_GATE_EN);

	}

	enable = !!(hdev->clock_gating_mask & (BIT_ULL(GAUDI_ENGINE_ID_MME_0)));

	WREG32(mmMME0_QM_CGM_CFG1, enable ? QMAN_CGM1_PWR_GATE_EN : 0);

	WREG32(mmMME0_QM_CGM_CFG, enable ? QMAN_COMMON_CP_CGM_PWR_GATE_EN : 0);



	if (hdev->clock_gating_mask & (BIT_ULL(GAUDI_ENGINE_ID_MME_2))) {

		WREG32(mmMME2_QM_CGM_CFG1, QMAN_CGM1_PWR_GATE_EN);

		WREG32(mmMME2_QM_CGM_CFG, QMAN_COMMON_CP_CGM_PWR_GATE_EN);

	}

	enable = !!(hdev->clock_gating_mask & (BIT_ULL(GAUDI_ENGINE_ID_MME_2)));

	WREG32(mmMME2_QM_CGM_CFG1, enable ? QMAN_CGM1_PWR_GATE_EN : 0);

	WREG32(mmMME2_QM_CGM_CFG, enable ? QMAN_COMMON_CP_CGM_PWR_GATE_EN : 0);



	for (i = 0, qman_offset = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) {

		if (!(hdev->clock_gating_mask &

					(BIT_ULL(GAUDI_ENGINE_ID_TPC_0 + i))))

			continue;

		enable = !!(hdev->clock_gating_mask &

				(BIT_ULL(GAUDI_ENGINE_ID_TPC_0 + i)));



		WREG32(mmTPC0_QM_CGM_CFG1 + qman_offset,

				QMAN_CGM1_PWR_GATE_EN);

				enable ? QMAN_CGM1_PWR_GATE_EN : 0);

		WREG32(mmTPC0_QM_CGM_CFG + qman_offset,

				QMAN_COMMON_CP_CGM_PWR_GATE_EN);

				enable ? QMAN_COMMON_CP_CGM_PWR_GATE_EN : 0);



		qman_offset += TPC_QMAN_OFFSET;

	}

CRA Git | Maintained and supported by SUSTech CRA and CCSE