Commit f43f97a0 authored by yong.liang's avatar yong.liang Committed by Wim Van Sebroeck
Browse files

dt-bindings: mediatek: mt8183: Add #reset-cells 



Add #reset-cells property and update example

Signed-off-by: default avataryong.liang <yong.liang@mediatek.com>
Signed-off-by: default avatarJiaxin Yu <jiaxin.yu@mediatek.com>
Reviewed-by: default avatarYingjoe Chen <yingjoe.chen@mediatek.com>
Reviewed-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarGuenter Roeck <groeck7@gmail.com>
Link: https://lore.kernel.org/r/20200115085828.27791-2-yong.liang@mediatek.com


Signed-off-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarWim Van Sebroeck <wim@linux-watchdog.org>
parent c514430c

Documentation/devicetree/bindings/watchdog/mtk-wdt.txt

+7 −3
Original line number Diff line number Diff line
@@ -9,17 +9,21 @@ Required properties: 
	"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622

	"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623

	"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629

	"mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183

	"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516



- reg : Specifies base physical address and size of the registers.



Optional properties:

- timeout-sec: contains the watchdog timeout in seconds.

- #reset-cells: Should be 1.



Example:



wdt: watchdog@10000000 {

	compatible = "mediatek,mt6589-wdt";

	reg = <0x10000000 0x18>;

watchdog: watchdog@10007000 {

	compatible = "mediatek,mt8183-wdt",

		     "mediatek,mt6589-wdt";

	reg = <0 0x10007000 0 0x100>;

	timeout-sec = <10>;

	#reset-cells = <1>;

};

include/dt-bindings/reset-controller/mt8183-resets.h

+17 −0
Original line number Diff line number Diff line
@@ -78,4 +78,21 @@ 
#define MT8183_INFRACFG_AO_I2C7_SW_RST				126

#define MT8183_INFRACFG_AO_I2C8_SW_RST				127



#define MT8183_INFRACFG_SW_RST_NUM				128



#define MT8183_TOPRGU_MM_SW_RST					1

#define MT8183_TOPRGU_MFG_SW_RST				2

#define MT8183_TOPRGU_VENC_SW_RST				3

#define MT8183_TOPRGU_VDEC_SW_RST				4

#define MT8183_TOPRGU_IMG_SW_RST				5

#define MT8183_TOPRGU_MD_SW_RST					7

#define MT8183_TOPRGU_CONN_SW_RST				9

#define MT8183_TOPRGU_CONN_MCU_SW_RST				12

#define MT8183_TOPRGU_IPU0_SW_RST				14

#define MT8183_TOPRGU_IPU1_SW_RST				15

#define MT8183_TOPRGU_AUDIO_SW_RST				17

#define MT8183_TOPRGU_CAMSYS_SW_RST				18



#define MT8183_TOPRGU_SW_RST_NUM				19



#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */

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