Commit f4224a4c authored by Pankaj Bharadiya's avatar Pankaj Bharadiya Committed by Jani Nikula
Browse files

drm/i915/display: Make WARN* drm specific where drm_device ptr is available 



drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.

Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.

The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.

@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}

@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}

@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}

@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}

Signed-off-by: default avatarPankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200128181603.27767-20-pankaj.laxminarayan.bharadiya@intel.com
parent 8afb2928

drivers/gpu/drm/i915/display/intel_atomic.c

+4 −2
Original line number Diff line number Diff line
@@ -318,7 +318,8 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta 
		}

	}



	if (WARN(*scaler_id < 0, "Cannot find scaler for %s:%d\n", name, idx))

	if (drm_WARN(&dev_priv->drm, *scaler_id < 0,

		     "Cannot find scaler for %s:%d\n", name, idx))

		return;



	/* set scaler mode */
@@ -469,7 +470,8 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, 
			idx = plane->base.id;



			/* plane on different crtc cannot be a scaler user of this crtc */

			if (WARN_ON(intel_plane->pipe != intel_crtc->pipe))

			if (drm_WARN_ON(&dev_priv->drm,

					intel_plane->pipe != intel_crtc->pipe))

				continue;



			plane_state = intel_atomic_get_new_plane_state(intel_state,

drivers/gpu/drm/i915/display/intel_bios.c

+6 −4
Original line number Diff line number Diff line
@@ -228,7 +228,7 @@ parse_panel_options(struct drm_i915_private *dev_priv, 


	ret = intel_opregion_get_panel_type(dev_priv);

	if (ret >= 0) {

		WARN_ON(ret > 0xf);

		drm_WARN_ON(&dev_priv->drm, ret > 0xf);

		panel_type = ret;

		drm_dbg_kms(&dev_priv->drm, "Panel type: %d (OpRegion)\n",

			    panel_type);
@@ -1248,7 +1248,8 @@ static int get_init_otp_deassert_fragment_len(struct drm_i915_private *dev_priv) 
	const u8 *data = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];

	int index, len;



	if (WARN_ON(!data || dev_priv->vbt.dsi.seq_version != 1))

	if (drm_WARN_ON(&dev_priv->drm,

			!data || dev_priv->vbt.dsi.seq_version != 1))

		return 0;



	/* index = 1 to skip sequence byte */
@@ -2305,7 +2306,8 @@ bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port por 
	}



	/* FIXME maybe deal with port A as well? */

	if (WARN_ON(port == PORT_A) || port >= ARRAY_SIZE(port_mapping))

	if (drm_WARN_ON(&dev_priv->drm,

			port == PORT_A) || port >= ARRAY_SIZE(port_mapping))

		return false;



	list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) {
@@ -2555,7 +2557,7 @@ intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915, 
	const struct child_device_config *child =

		i915->vbt.ddi_port_info[port].child;



	if (WARN_ON_ONCE(!IS_GEN9_LP(i915)))

	if (drm_WARN_ON_ONCE(&i915->drm, !IS_GEN9_LP(i915)))

		return false;



	return child && child->hpd_invert;

drivers/gpu/drm/i915/display/intel_bw.c

+2 −1
Original line number Diff line number Diff line
@@ -122,7 +122,8 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, 
	if (ret)

		return ret;



	if (WARN_ON(qi->num_points > ARRAY_SIZE(qi->points)))

	if (drm_WARN_ON(&dev_priv->drm,

			qi->num_points > ARRAY_SIZE(qi->points)))

		qi->num_points = ARRAY_SIZE(qi->points);



	for (i = 0; i < qi->num_points; i++) {

drivers/gpu/drm/i915/display/intel_color.c

+2 −1
Original line number Diff line number Diff line
@@ -309,7 +309,8 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state) 
		 * LUT is needed but CSC is not we need to load an

		 * identity matrix.

		 */

		WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_GEMINILAKE(dev_priv));

		drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) &&

			    !IS_GEMINILAKE(dev_priv));



		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,

				    ilk_csc_coeff_identity,

drivers/gpu/drm/i915/display/intel_combo_phy.c

+1 −1
Original line number Diff line number Diff line
@@ -256,7 +256,7 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, 
	u32 val;



	if (is_dsi) {

		WARN_ON(lane_reversal);

		drm_WARN_ON(&dev_priv->drm, lane_reversal);



		switch (lane_count) {

		case 1:

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