Commit f40ac0f3 authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Felix Fietkau
Browse files

mt76: mt7615: introduce mt7663e support 



Introduce support for mt7663e 802.11ac 2x2:2 chipset to mt7615 driver.

Co-developed-by: default avatarSean Wang <sean.wang@mediatek.com>
Signed-off-by: default avatarSean Wang <sean.wang@mediatek.com>
Co-developed-by: default avatarRyder Lee <ryder.lee@mediatek.com>
Signed-off-by: default avatarRyder Lee <ryder.lee@mediatek.com>
Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent 8327cd82

drivers/net/wireless/mediatek/mt76/mt7615/dma.c

+46 −4
Original line number Diff line number Diff line
@@ -101,8 +101,12 @@ void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 
	__le32 *rxd = (__le32 *)skb->data;

	__le32 *end = (__le32 *)&skb->data[skb->len];

	enum rx_pkt_type type;

	u16 flag;



	type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));

	flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0]));

	if (type == PKT_TYPE_RX_EVENT && flag == 0x1)

		type = PKT_TYPE_NORMAL_MCU;



	switch (type) {

	case PKT_TYPE_TXS:
@@ -116,6 +120,7 @@ void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 
	case PKT_TYPE_RX_EVENT:

		mt7615_mcu_rx_event(dev, skb);

		break;

	case PKT_TYPE_NORMAL_MCU:

	case PKT_TYPE_NORMAL:

		if (!mt7615_mac_fill_rx(dev, skb)) {

			mt76_rx(&dev->mt76, q, skb);
@@ -186,6 +191,41 @@ static void mt7622_dma_sched_init(struct mt7615_dev *dev) 
	mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET1, 0xedcba987);

}



static void mt7663_dma_sched_init(struct mt7615_dev *dev)

{

	int i;



	mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE),

		 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,

		 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |

		 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));



	/* enable refill control group 0, 1, 2, 4, 5 */

	mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffc80000);

	/* enable group 0, 1, 2, 4, 5, 15 */

	mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x70068037);



	/* each group min quota must larger then PLE_PKT_MAX_SIZE_NUM */

	for (i = 0; i < 5; i++)

		mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)),

			FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |

			FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));

	mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(5)),

		FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |

		FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x40));

	mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(15)),

		FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x20) |

		FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x20));



	mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210);

	mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210);

	mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x00050005);

	mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(3)), 0);

	/* ALTX0 and ALTX1 QID mapping to group 5 */

	mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET0), 0x6012345f);

	mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET1), 0xedcba987);

}



int mt7615_dma_init(struct mt7615_dev *dev)

{

	int rx_ring_size = MT7615_RX_RING_SIZE;
@@ -198,10 +238,6 @@ int mt7615_dma_init(struct mt7615_dev *dev) 
		MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN |

		MT_WPDMA_GLO_CFG_OMIT_TX_INFO);



	if (!is_mt7622(&dev->mt76))

		mt76_set(dev, MT_WPDMA_GLO_CFG,

			 MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY);



	mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,

		       MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1);
@@ -215,6 +251,9 @@ int mt7615_dma_init(struct mt7615_dev *dev) 
		       MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3);



	if (is_mt7615(&dev->mt76)) {

		mt76_set(dev, MT_WPDMA_GLO_CFG,

			 MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY);



		mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1);

		mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000);

		mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000);
@@ -271,6 +310,9 @@ int mt7615_dma_init(struct mt7615_dev *dev) 
	if (is_mt7622(&dev->mt76))

		mt7622_dma_sched_init(dev);



	if (is_mt7663(&dev->mt76))

		mt7663_dma_sched_init(dev);



	return 0;

}

drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c

+28 −12
Original line number Diff line number Diff line
@@ -128,11 +128,16 @@ mt7615_eeprom_parse_hw_band_cap(struct mt7615_dev *dev) 
static void mt7615_eeprom_parse_hw_cap(struct mt7615_dev *dev)

{

	u8 *eeprom = dev->mt76.eeprom.data;

	u8 tx_mask, max_nss;

	u32 val;

	u8 tx_mask;



	mt7615_eeprom_parse_hw_band_cap(dev);



	if (is_mt7663(&dev->mt76)) {

		tx_mask = 2;

	} else {

		u8 max_nss;

		u32 val;



		/* read tx-rx mask from eeprom */

		val = mt76_rr(dev, MT_TOP_STRAP_STA);

		max_nss = val & MT_TOP_3NSS ? 3 : 4;
@@ -141,6 +146,7 @@ static void mt7615_eeprom_parse_hw_cap(struct mt7615_dev *dev) 
				     eeprom[MT_EE_NIC_CONF_0]);

		if (!tx_mask || tx_mask > max_nss)

			tx_mask = max_nss;

	}



	dev->chainmask = BIT(tx_mask) - 1;

	dev->mphy.antenna_mask = dev->chainmask;
@@ -247,6 +253,18 @@ static void mt7622_apply_cal_free_data(struct mt7615_dev *dev) 
	}

}



static void mt7615_cal_free_data(struct mt7615_dev *dev)

{

	switch (mt76_chip(&dev->mt76)) {

	case 0x7622:

		mt7622_apply_cal_free_data(dev);

		break;

	case 0x7615:

		mt7615_apply_cal_free_data(dev);

		break;

	}

}



int mt7615_eeprom_init(struct mt7615_dev *dev)

{

	int ret;
@@ -259,10 +277,8 @@ int mt7615_eeprom_init(struct mt7615_dev *dev) 
	if (ret && dev->mt76.otp.data)

		memcpy(dev->mt76.eeprom.data, dev->mt76.otp.data,

		       MT7615_EEPROM_SIZE);

	else if (is_mt7622(&dev->mt76))

		mt7622_apply_cal_free_data(dev);

	else

		mt7615_apply_cal_free_data(dev);

		mt7615_cal_free_data(dev);



	mt7615_eeprom_parse_hw_cap(dev);

	memcpy(dev->mt76.macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,

drivers/net/wireless/mediatek/mt76/mt7615/init.c

+14 −4
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 * Author: Roy Luo <royluo@google.com>

 *         Ryder Lee <ryder.lee@mediatek.com>

 *         Felix Fietkau <nbd@nbd.name>

 *         Lorenzo Bianconi <lorenzo@kernel.org>

 */



#include <linux/etherdevice.h>
@@ -77,7 +78,6 @@ static void mt7615_mac_init(struct mt7615_dev *dev) 
	int i;



	mt7615_init_mac_chain(dev, 0);

	mt7615_init_mac_chain(dev, 1);



	mt76_rmw_field(dev, MT_TMAC_CTCR0,

		       MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f);
@@ -101,15 +101,25 @@ static void mt7615_mac_init(struct mt7615_dev *dev) 
		FIELD_PREP(MT_AGG_ARCR_RATE_DOWN_RATIO, 1) |

		FIELD_PREP(MT_AGG_ARCR_RATE_UP_EXTRA_TH, 4));



	mt76_wr(dev, MT_DMA_DCR0, MT_DMA_DCR0_RX_VEC_DROP |

		FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 3072));



	for (i = 0; i < MT7615_WTBL_SIZE; i++)

		mt7615_mac_wtbl_update(dev, i,

				       MT_WTBL_UPDATE_ADM_COUNT_CLEAR);



	mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_EN);

	mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_EN);



	/* disable hdr translation and hw AMSDU */

	mt76_wr(dev, MT_DMA_DCR0,

		FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 3072) |

		MT_DMA_DCR0_RX_VEC_DROP);

	if (is_mt7663(&dev->mt76)) {

		mt76_wr(dev, MT_CSR(0x010), 0x8208);

		mt76_wr(dev, 0x44064, 0x2000000);

		mt76_wr(dev, MT_WF_AGG(0x160), 0x5c341c02);

		mt76_wr(dev, MT_WF_AGG(0x164), 0x70708040);

	} else {

		mt7615_init_mac_chain(dev, 1);

	}

}



bool mt7615_wait_for_mcu_init(struct mt7615_dev *dev)

drivers/net/wireless/mediatek/mt76/mt7615/mac.c

+6 −0
Original line number Diff line number Diff line
@@ -1524,6 +1524,9 @@ void mt7615_mac_set_scs(struct mt7615_dev *dev, bool enable) 
	if (dev->scs_en == enable)

		goto out;



	if (is_mt7663(&dev->mt76))

		goto out;



	if (enable) {

		mt76_set(dev, MT_WF_PHY_MIN_PRI_PWR(0),

			 MT_WF_PHY_PD_BLK(0));
@@ -1555,6 +1558,9 @@ void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy) 
{

	u32 rxtd;



	if (is_mt7663(&dev->mt76))

		return;



	if (ext_phy)

		rxtd = MT_WF_PHY_RXTD2(10);

	else

drivers/net/wireless/mediatek/mt76/mt7615/mac.h

+10 −1
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#define MT_CT_DMA_BUF_NUM		2



#define MT_RXD0_LENGTH			GENMASK(15, 0)

#define MT_RXD0_PKT_FLAG                GENMASK(19, 16)

#define MT_RXD0_PKT_TYPE		GENMASK(31, 29)



#define MT_RXD0_NORMAL_ETH_TYPE_OFS	GENMASK(22, 16)
@@ -26,7 +27,8 @@ enum rx_pkt_type { 
	PKT_TYPE_RX_TMR,

	PKT_TYPE_RETRIEVE,

	PKT_TYPE_TXRX_NOTIFY,

	PKT_TYPE_RX_EVENT

	PKT_TYPE_RX_EVENT,

	PKT_TYPE_NORMAL_MCU,

};



#define MT_RXD1_NORMAL_BSSID		GENMASK(31, 26)
@@ -229,8 +231,15 @@ enum tx_phy_bandwidth { 
#define MT_TXD6_FIXED_BW		BIT(2)

#define MT_TXD6_BW			GENMASK(1, 0)



/* MT7663 DW7 HW-AMSDU */

#define MT_TXD7_HW_AMSDU_CAP		BIT(30)

#define MT_TXD7_TYPE			GENMASK(21, 20)

#define MT_TXD7_SUB_TYPE		GENMASK(19, 16)

#define MT_TXD7_SPE_IDX			GENMASK(15, 11)

#define MT_TXD7_SPE_IDX_SLE		BIT(10)



#define MT_TXD8_L_TYPE			GENMASK(5, 4)

#define MT_TXD8_L_SUB_TYPE		GENMASK(3, 0)



#define MT_TX_RATE_STBC			BIT(11)

#define MT_TX_RATE_NSS			GENMASK(10, 9)

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