Commit f403a26c authored by Leonard Crestez's avatar Leonard Crestez Committed by Shawn Guo
Browse files

arm64: dts: imx8mm: Add cpu speed grading and all OPPs 



Add a nvmem cell on cpu node referencing speed grade and the 1.8 Ghz
cpufreq opp.

Signed-off-by: default avatarLeonard Crestez <leonard.crestez@nxp.com>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 78cc25fa

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+16 −1
Original line number Diff line number Diff line
@@ -53,6 +53,8 @@ 
			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			operating-points-v2 = <&a53_opp_table>;

			nvmem-cells = <&cpu_speed_grade>;

			nvmem-cell-names = "speed_grade";

		};



		A53_1: cpu@1 {
@@ -100,14 +102,23 @@ 
		opp-1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <850000>;

			opp-supported-hw = <0xe>, <0x7>;

			clock-latency-ns = <150000>;

		};



		opp-1600000000 {

			opp-hz = /bits/ 64 <1600000000>;

			opp-microvolt = <900000>;

			opp-supported-hw = <0xc>, <0x7>;

			clock-latency-ns = <150000>;

		};



		opp-1800000000 {

			opp-hz = /bits/ 64 <1800000000>;

			opp-microvolt = <1000000>;

			/* Consumer only but rely on speed grading */

			opp-supported-hw = <0x8>, <0x7>;

			clock-latency-ns = <150000>;

			opp-suspend;

		};

	};
@@ -319,6 +330,10 @@ 
				/* For nvmem subnodes */

				#address-cells = <1>;

				#size-cells = <1>;



				cpu_speed_grade: speed-grade@10 {

					reg = <0x10 4>;

				};

			};



			anatop: anatop@30360000 {

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