Commit f3f0d951 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer Committed by Ralf Baechle
Browse files

MIPS: R46000: Fix Micro-assembler field overflow for R4600 V2 



Fix uasm warning, which triggered because of workaround for R4600 V2 CPUs.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6716/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 57c7ea51

arch/mips/mm/page.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -273,7 +273,7 @@ void build_clear_page(void) 
		uasm_i_ori(&buf, A2, A0, off);

		uasm_i_ori(&buf, A2, A0, off);





	if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())

	if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())

		uasm_i_lui(&buf, AT, 0xa000);

		uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));





	off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)

	off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)

				* cache_line_size : 0;

				* cache_line_size : 0;
@@ -424,7 +424,7 @@ void build_copy_page(void) 
		uasm_i_ori(&buf, A2, A0, off);

		uasm_i_ori(&buf, A2, A0, off);





	if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())

	if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())

		uasm_i_lui(&buf, AT, 0xa000);

		uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));





	off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *

	off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *

				cache_line_size : 0;

				cache_line_size : 0;

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