Unverified Commit f3e182c3 authored by Sowjanya Komatineni's avatar Sowjanya Komatineni Committed by Mark Brown
Browse files

spi: tegra114: de-assert CS before SPI mode change 



With SW CS, during the transfer completion CS is de-asserted by writing
default command1 register value to SPI_COMMAND1 register. With this both
mode and CS state are set at the same time and if current transfer mode
is different to default SPI mode and if mode change happens prior to CS
de-assert, clock polarity can change while CS is active before transfer
finishes.

This causes Slave to see spurious clock edges resulting in data mismatch.

This patch fixes this by de-asserting CS before writing SPI_COMMAND1 to
its default value so through out the transfer it will be in same SPI mode.

Signed-off-by: default avatarSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 1723fdec

drivers/spi/spi-tegra114.c

+16 −6
Original line number Diff line number Diff line
@@ -856,6 +856,19 @@ static void tegra_spi_transfer_delay(int delay) 
	udelay(delay % 1000);

}



static void tegra_spi_transfer_end(struct spi_device *spi)

{

	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);

	int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;



	if (cs_val)

		tspi->command1_reg |= SPI_CS_SW_VAL;

	else

		tspi->command1_reg &= ~SPI_CS_SW_VAL;

	tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);

	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);

}



static int tegra_spi_transfer_one_message(struct spi_master *master,

			struct spi_message *msg)

{
@@ -918,8 +931,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, 


complete_xfer:

		if (ret < 0 || skip) {

			tegra_spi_writel(tspi, tspi->def_command1_reg,

					SPI_COMMAND1);

			tegra_spi_transfer_end(spi);

			tegra_spi_transfer_delay(xfer->delay_usecs);

			goto exit;

		} else if (list_is_last(&xfer->transfer_list,
@@ -927,13 +939,11 @@ complete_xfer: 
			if (xfer->cs_change)

				tspi->cs_control = spi;

			else {

				tegra_spi_writel(tspi, tspi->def_command1_reg,

						SPI_COMMAND1);

				tegra_spi_transfer_end(spi);

				tegra_spi_transfer_delay(xfer->delay_usecs);

			}

		} else if (xfer->cs_change) {

			tegra_spi_writel(tspi, tspi->def_command1_reg,

					SPI_COMMAND1);

			tegra_spi_transfer_end(spi);

			tegra_spi_transfer_delay(xfer->delay_usecs);

		}

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